Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

6.1.10. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals

Figure 57. 10/100/1000 Ethernet MAC Function with Internal FIFO Buffers, and 1000BASE-X/SGMII PCS With Embedded PMA Signals


Note to 10/100/1000 Ethernet MAC Function with Internal FIFO Buffers, and 1000BASE-X/SGMII PCS With Embedded PMA Signals:

  1. The SERDES control signals are present in variations targeting devices with GX transceivers. For device families prior to the Stratix® V device, the reconfiguration signals—reconfig_clk, reconfig_togxb, and reconfig_fromgxb—are always present in the interface. For Stratix® V GX device, the reconfiguration signals—reconfig_togxb and reconfig_fromgxb—are always present in the interface. The reconfig_clk reconfiguration signal is embedded in the reconfig_togxb reconfiguration signal. For Intel® Arria® 10 GX device, the reconfig_avmm interface signal is present when reconfiguration feature is enabled.
  2. The DATAWIDTH value depends on the FIFO width that you select in the parameter editor. Options available are 8 and 32 bits.

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