Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

5.2.4. An_Expansion Register (Word Offset 0x06)

Table 53.  An_Expansion Register Description
Bit(s) Name R/W Description
0 LINK_PARTNER_AUTO_NEGOTIATION_ABLE RO A value of 1 indicates that the link partner supports auto-negotiation. The reset value is 0.
1 PAGE_RECEIVE RO A value of 1 indicates that a new page is received with new partner ability available in the register partner_ability. The bit is set to 0 (reset value) when the system management agent performs a read access.
2 NEXT_PAGE_ABLE Unused. Always set to 0.
15:3 Reserved

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