Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

1.5. High-Level Block Diagrams

High-level block diagrams of different variations of the Triple-Speed Ethernet Intel® FPGA IP.
Figure 1. 10/100/1000 Mbps Ethernet MAC


Figure 2. Multiport MAC


Figure 3. 10/100/1000 Mbps Ethernet MAC and 1000BASE-X/SGMII PCS with Optional PMA


Figure 4. 10/100/1000 Mbps Ethernet MAC and 1000BASE-X/SGMII 2XTBI PCS with PMA
Figure 5. 10/100/1000 Mbps Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS
Figure 6. 1000BASE-X/SGMII PCS with Optional PMA


Figure 7. 1000BASE-X/SGMII 2XTBI PCS
Figure 8. Standalone 10/100/1000 Mbps Ethernet MAC


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