Triple-Speed Ethernet Intel® FPGA IP User Guide

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ID 683402
Date 5/30/2022
Public
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6.1.10.3. Intel® Arria® 10 Transceiver Native PHY Signals

Table 94.   Intel® Arria® 10 Transceiver Native PHY Signals
Name I/O Description
tx_serial_clk I Serial clock input from the transceiver PLL. The frequency of this clock is 1250 MHz and the division factor is fixed to divide by 2.
rx_cdr_refclk I Reference clock input to the receive clock data recovery (CDR) circuitry. The frequency of this clock is 125 MHz.
tx_analogreset I Resets the analog transmit portion of the transceiver PHY.
tx_digitalreset I Resets the digital transmit portion of the transceiver PHY.
rx_analogreset I Resets the analog receive portion of the transceiver PHY.
rx_digitalreset I Resets the digital receive portion of the transceiver PHY.
tx_cal_busy O When asserted, this signal indicates that the transmit channel is being calibrated.
rx_cal_busy O When asserted, this signal indicates that the receive channel is being calibrated.
rx_set_locktodata I Force the receiver CDR to lock to the incoming data.
rx_set_locktoref I Force the receiver CDR to lock to the phase and frequency of the input reference clock.
rx_is_lockedtodata O When asserted, this signal indicates that the CDR PLL is locked to the incoming data rx_serial_data.
rx_is_lockedtoref O When asserted, this signal indicates that the CDR PLL is locked to the incoming reference clock, rx_cdr_refclk.

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