Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

5.2.3.1. 1000BASE-X

Table 50.  Dev_Ability and Partner_Ability Registers Bits Description in 1000BASE-X
Bit(s) Name R/W Description
0:4 Reserved Always set these bits to 0.
5 FD RW/RO (1), (2) Full-duplex mode enable. A value of 1 indicates support for full duplex.
6 HD Half-duplex mode enable. A value of 1 indicates support for half duplex.
7 PS1 Pause support.
  • PS1=0 / PS2=0: Pause is not supported.
  • PS1=0 / PS2=1: Asymmetric pause toward link partner.
  • PS1=1 / PS2=0: Symmetric pause.
  • PS1=1/ PS2=1: Pause is supported on transmit and receive.
8 PS2
9:11 Reserved Always set these bits to 0.
12 RF1 RW/RO (1), (2) Remote fault condition:
  • RF1=0 / RF2=0: No error, link is valid (reset condition).
  • RF1=0 / RF2=1: Offline.
  • RF1=1 / RF2=0: Failure condition.
  • RF1=1 / RF2=1: Auto-negotiation error.
13 RF2
14 ACK RO Acknowledge. A value of 1 indicates that the device has received three consecutive matching ability values from its link partner.
15 NP RW/RO(1) (2) Next page. In dev_ability register, this bit is always set to 0.
Notes to Dev_Ability and Partner_Ability Registers Bits Description in 1000BASE-X :
  1. All bits in the dev_ability register have RW access.
  2. All bits in the partner_ability register are read-only.

Did you find the information on this page useful?

Characters remaining:

Feedback Message