Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 7/22/2024
Public
Document Table of Contents

7.1.1. MAC and PCS With GX Transceivers

In configurations that contain the MAC, PCS, and GX transceivers, you have the following options in optimizing clock resources:
  • Utilize the same reset signal for all MAC instances if you do not require a separate reset for each instance.
  • Utilize the same reference clock for all PMA quads
  • Utilize the same clock source to drive the reference clock, FIFO transmit and receive clocks, and system clocks, if these clocks run at the same frequency.

The Quartus® Prime software automatically optimizes the TBI transmit clocks. Only one clock source drives the TBI transmit clocks from each PMA quad.

The calibration clock (gxb_cal_blk_clk) calibrates the termination resistors in all transceiver channels in a device. As there is only one calibration circuit in each device, one clock source suffices.

Note:

If you do not constrain the PLL inputs and outputs in your design, add derive_pll_clocks in the timing constraint file to ensure that the Timing Analyzer automatically creates derived clocks for the PLL outputs.

Figure 79. Clock Distribution in MAC and SGMII PCS with GXB Configuration—Optimal CaseFigure shows the optimal clock distribution scheme you can achieve in configurations that contain the 10/100/1000 Ethernet MAC, SGMII PCS, and GX transceivers.


In addition to the aforementioned optimization options, the TBI transmit and receive clocks can be used to drive the MAC transmit and receive clocks, respectively.

Figure 80. Clock Distribution in MAC and 1000BASE-X PCS with GXB Configuration—Optimal CaseFigure shows the optimal clock distribution scheme you can achieve in configurations that contain the 10/100/1000 Ethernet MAC, 1000Base-X PCS, and GX transceivers.