External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

3.23. Memory Mapped Register (MMR) Tables

The address buses to read and write from the MMR registers are 10 bits wide, while the read and write data buses are configured to be 32 bits. The Bits Register Link column in the table below provides the mapping on the width of the data read within the 32-bit bus. The reads and writes are always performed using the 32-bit-wide bus.

Register Summary

Register Address 32-bit Bus Bits Register link
sbcfg8 7 16
sbcfg9 8 16
reserve2 9 16
ctrlcfg0 10 32
ctrlcfg1 11 32
ctrlcfg2 12 32
ctrlcfg3 13 32
ctrlcfg4 14 32
ctrlcfg5 15 16
ctrlcfg6 16 16
ctrlcfg7 17 16
ctrlcfg8 18 8
ctrlcfg9 19 8
dramtiming0 20 24
dramodt0 21 32
dramodt1 22 24
sbcfg0 23 32
sbcfg1 24 32
sbcfg2 25 8
sbcfg3 26 24
sbcfg4 27 24
sbcfg5 28 8
sbcfg6 29 32
sbcfg7 30 8
caltiming0 31 32
caltiming1 32 32
caltiming2 33 32
caltiming3 34 32
caltiming4 35 32
caltiming5 36 24
caltiming6 37 32
caltiming7 38 32
caltiming8 39 32
caltiming9 40 8
caltiming10 41 8
dramaddrw 42 24
sideband0 43 8
sideband1 44 8
sideband2 45 8
sideband3 46 8
sideband4 47 8
sideband5 48 8
sideband6 49 8
sideband7 50 8
sideband8 51 8
sideband9 52 8
sideband10 53 8
sideband11 54 8
sideband12 55 8
sideband13 56 32
sideband14 57 16
sideband15 58 8
dramsts 59 8
dbgdone 60 8
dbgsignals 61 32
dbgreset 62 8
dbgmatch 63 32
counter0mask 64 32
counter1mask 65 32
counter0match 66 32
counter1match 67 32
niosreserve0 68 16
niosreserve1 69 16
niosreserve2 70 16
ecc1 128 10
ecc2 129 22
ecc3 130 9
ecc4 144 16
Note: Addresses are in decimal format.

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