External Memory Interface Handbook Volume 3: Reference Material: For UniPHY-based Device Families

ID 683841
Date 3/06/2023
Public
Document Table of Contents

3.23.3. ctrlcfg2: Controller Configuration

address=12(32 bit)

Field Bit High Bit Low Description Access
cfg_ctrl_output_regd 0 0 Set to one to register the HMC command output. Set to 0 to disable it. Read/Write
cfg_dbc0_output_regd 1 1 Set to one to register the HMC command output. Set to 0 to disable it. Read/Write
cfg_dbc1_output_regd 2 2 Set to one to register the HMC command output. Set to 0 to disable it. Read/Write
cfg_dbc2_output_regd 3 3 Set to one to register the HMC command output. Set to 0 to disable it. Read/Write
cfg_dbc3_output_regd 4 4 Set to one to register the HMC command output. Set to 0 to disable it. Read/Write
cfg_ctrl2dbc_switch0 6 5 Select of the MUX ctrl2dbc_switch0. 2 Read/Write
cfg_ctrl2dbc_switch1 8 7 Select of the MUX ctrl2dbc_switch1. 2 Read/Write
cfg_dbc0_ctrl_sel 9 9 DBC0 - control path select. 1 Read/Write
cfg_dbc1_ctrl_sel 10 10 DBC1 - control path select. 1 Read/Write
cfg_dbc2_ctrl_sel 11 11 DBC2 - control path select. 1 Read/Write
cfg_dbc3_ctrl_sel 12 12 DBC3 - control path select. 1 Read/Write
cfg_dbc2ctrl_sel 14 13 Specifies which DBC is driven by the local control path. 2 Read/Write
cfg_dbc0_pipe_lat 17 15 Specifies in number of controller clock cycles the latency of pipelining the signals from control path to DBC0 Read/Write
cfg_dbc1_pipe_lat 20 18 Specifies in number of controller clock cycles the latency of pipelining the signals from control path to DBC1 Read/Write
cfg_dbc2_pipe_lat 23 21 Specifies in number of controller clock cycles the latency of pipelining the signals from control path to DBC2 Read/Write
cfg_dbc3_pipe_lat 26 24 Specifies in number of controller clock cycles the latency of pipelining the signals from control path to DBC3 Read/Write