External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

3.23.35. dramaddrw: Row/Column/Bank Address Width Configuration

address=42(32 bit)

Field Bit High Bit Low Description Access
cfg_col_addr_width 4 0 The number of column address bits for the memory devices in your memory interface. Read/Write
cfg_row_addr_width 9 5 The number of row address bits for the memory devices in your memory interface. Read/Write
cfg_bank_addr_width 13 10 The number of bank address bits for the memory devices in your memory interface. Read/Write
cfg_bank_group_addr_width 15 14 The number of bank group address bits for the memory devices in your memory interface. Read/Write
cfg_cs_addr_width 18 16 The number of chip select address bits for the memory devices in your memory interface. Read/Write

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