External Memory Interface Handbook Volume 3: Reference Material: For UniPHY-based Device Families

ID 683841
Date 3/06/2023
Document Table of Contents

3.23.24. caltiming0: Command/Address/Latency Parameters

address=31(32 bit)

Field Bit High Bit Low Description Access
cfg_t_param_act_to_rdwr 5 0 Activate to Read/write command timing. Read/Write
cfg_t_param_act_to_pch 11 6 Active to precharge. Read/Write
cfg_t_param_act_to_act 17 12 Active to activate timing on same bank. Read/Write
cfg_t_param_act_to_act_diff_bank 23 18 Active to activate timing on different banks, for DDR4 same bank group. Read/Write
cfg_t_param_act_to_act_diff_bg 29 24 Active to activate timing on different bank groups, DDR4 only. Read/Write