External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

3.23.2. ctrlcfg1: Controller Configuration

address=11(32 bit)

Field Bit High Bit Low Description Access
cfg_dbc3_burst_length 4 0 Configures burst length for DBC3. Legal values are valid for JEDEC allowed DRAM values for the DRAM selected in cfg_type. For DDR3, DDR4 and LPDDR3, this should be programmed with 8 (binary "01000"), for RLDRAM III it can be programmed with 2 or 4 or 8. Read/Write
cfg_addr_order 6 5 Selects the order for address interleaving. Programming this field with different values gives different mappings between the AXI or Avalon-MM address and the SDRAM address. Program this field with the following binary values to select the ordering. "00" - chip, row, bank(BG, BA), column; "01" - chip, bank(BG, BA), row, column; "10"-row, chip, bank(BG, BA), column. Read/Write
cfg_ctrl_enable_ecc 7 7 Enable the generation and checking of ECC. Read/Write
cfg_dbc0_enable_ecc 8 8 Enable the generation and checking of ECC. Read/Write
cfg_dbc1_enable_ecc 9 9 Enable the generation and checking of ECC. Read/Write
cfg_dbc2_enable_ecc 10 10 Enable the generation and checking of ECC. Read/Write
cfg_dbc3_enable_ecc 11 11 Enable the generation and checking of ECC. Read/Write
cfg_reorder_data 12 12 This bit controls whether the controller can re-order operations to optimize SDRAM bandwidth. It should generally be set to a one. Read/Write
cfg_ctrl_reorder_rdata 13 13 This bit controls whether the controller need to re-order the read return data. Read/Write
cfg_dbc0_reorder_rdata 14 14 This bit controls whether the controller need to re-order the read return data. Read/Write
cfg_dbc1_reorder_rdata 15 15 This bit controls whether the controller need to re-order the read return data. Read/Write
cfg_dbc2_reorder_rdata 16 16 This bit controls whether the controller need to re-order the read return data. Read/Write
cfg_dbc3_reorder_rdata 17 17 This bit controls whether the controller need to re-order the read return data. Read/Write
cfg_reorder_read 18 18 This bit controls whether the controller can re-order read command to 1. Read/Write
cfg_starve_limit 24 19 Specifies the number of DRAM burst transactions an individual transaction will allow to reorder ahead of it before its priority is raised in the memory controller. Read/Write
cfg_dqstrk_en 25 25 Enables DQS tracking in the PHY. Read/Write
cfg_ctrl_enable_dm 26 26 Set to a one to enable DRAM operation if DM pins are connected. Read/Write
cfg_dbc0_enable_dm 27 27 Set to a one to enable DRAM operation if DM pins are connected. Read/Write
cfg_dbc1_enable_dm 28 28 Set to a one to enable DRAM operation if DM pins are connected. Read/Write
cfg_dbc2_enable_dm 29 29 Set to a one to enable DRAM operation if DM pins are connected. Read/Write
cfg_dbc3_enable_dm 30 30 Set to a one to enable DRAM operation if DM pins are connected. Read/Write

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