External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

3.23.14. sbcfg0: Sideband Configuration

address=23(32 bit)

Field Bit High Bit Low Description Access
cfg_rld3_refresh_seq0 15 0 Banks to Refresh for RLD3 in sequence 0. Must not be more than 4 banks. Read/Write
cfg_rld3_refresh_seq1 31 16 Banks to Refresh for RLD3 in sequence 1. Must not be more than 4 banks. Read/Write

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