External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

3.23.13. dramodt1: On-Die Termination Parameters

address=22(32 bit)

Field Bit High Bit Low Description Access
cfg_wr_odt_on 5 0 Indicates number of memory clock cycle gap between write command and ODT signal rising edge. Read/Write
cfg_rd_odt_on 11 6 Indicates number of memory clock cycle gap between read command and ODT signal rising edge. Read/Write
cfg_wr_odt_period 17 12 Indicates number of memory clock cycle write ODT signal should stay asserted after rising edge. Read/Write
cfg_rd_odt_period 23 18 Indicates number of memory clock cycle read ODT signal should stay asserted after rising edge. Read/Write

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