External Memory Interface Handbook Volume 3: Reference Material

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ID 683841
Date 7/24/2019
Public
Document Table of Contents

3.23.11. dramtiming0: Timing Parameters

address=20(32 bit)

Field Bit High Bit Low Description Access
cfg_tcl 6 0 Memory read latency. Read/Write
cfg_power_saving_exit_cycles 12 7 The minimum number of cycles to stay in a low power state. This applies to both power down and self-refresh and should be set to the greater of tPD and tCKESR. Read/Write
cfg_mem_clk_disable_entry_cycles 18 13 Set to a the number of clocks after the execution of an self-refresh to stop the clock. This register is generally set based on PHY design latency and should generally not be changed. Read/Write

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