3.23.36. sideband0: Sideband

External Memory Interface Handbook Volume 3: Reference Material

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ID 683841

Date 7/24/2019

Version 17.0

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Document Table of Contents

1. Functional Description—UniPHY

1.1. I/O Pads 1.2. Reset and Clock Generation 1.3. Dedicated Clock Networks 1.4. Address and Command Datapath 1.5. Write Datapath 1.6. Read Datapath 1.7. Sequencer 1.8. Shadow Registers 1.9. UniPHY Interfaces 1.10. UniPHY Signals 1.11. PHY-to-Controller Interfaces 1.12. Using a Custom Controller 1.13. AFI 3.0 Specification 1.14. Register Maps 1.15. Ping Pong PHY 1.16. Efficiency Monitor and Protocol Checker 1.17. UniPHY Calibration Stages 1.18. Document Revision History

1.5. Write Datapath

1.5.1. Leveling Circuitry

1.7. Sequencer

1.7.1. Nios II-Based Sequencer 1.7.2. RTL-based Sequencer

1.7.1. Nios II-Based Sequencer

1.7.1.1. NIOS II-based Sequencer Function 1.7.1.2. Nios II-based Sequencer Architecture 1.7.1.3. Nios II-based Sequencer SCC Manager 1.7.1.4. NIOS II-based Sequencer RW Manager 1.7.1.5. NIOS II-based Sequencer PHY Manager 1.7.1.6. NIOS II-based Sequencer Data Manager 1.7.1.7. NIOS II-based Sequencer Tracking Manager 1.7.1.8. NIOS II-based Sequencer Processor 1.7.1.9. NIOS II-based Sequencer Calibration and Diagnostics

1.8. Shadow Registers

1.8.1. Shadow Registers Operation

1.9. UniPHY Interfaces

1.9.1. The DLL and PLL Sharing Interface 1.9.2. The OCT Sharing Interface

1.9.1. The DLL and PLL Sharing Interface

1.9.1.1. Sharing PLLs or DLLs 1.9.1.2. About PLL Simulation

1.9.2. The OCT Sharing Interface

1.9.2.1. Modifying the Pin Assignment Script for QDR II and RLDRAM II

1.13. AFI 3.0 Specification

1.13.1. Bus Width and AFI Ratio 1.13.2. AFI Parameters 1.13.3. AFI Signals

1.13.3. AFI Signals

1.13.3.1. AFI Clock and Reset Signals 1.13.3.2. AFI Address and Command Signals 1.13.3.3. AFI Write Data Signals 1.13.3.4. AFI Read Data Signals 1.13.3.5. AFI Calibration Status Signals 1.13.3.6. AFI Tracking Management Signals

1.14. Register Maps

1.14.1. UniPHY Register Map 1.14.2. Controller Register Map

1.15. Ping Pong PHY

1.15.1. Ping Pong PHY Feature Description 1.15.2. Ping Pong PHY Architecture 1.15.3. Ping Pong PHY Operation

1.15.2. Ping Pong PHY Architecture

1.15.2.1. Ping Pong Gasket 1.15.2.2. Ping Pong PHY Calibration

1.16. Efficiency Monitor and Protocol Checker

1.16.1. Efficiency Monitor 1.16.2. Protocol Checker 1.16.3. Read Latency Counter 1.16.4. Using the Efficiency Monitor and Protocol Checker 1.16.5. Avalon CSR Slave and JTAG Memory Map

1.17. UniPHY Calibration Stages

1.17.1. Calibration Overview 1.17.2. Calibration Stages 1.17.3. Memory Initialization 1.17.4. Stage 1: Read Calibration Part One—DQS Enable Calibration and DQ/DQS Centering 1.17.5. Stage 2: Write Calibration Part One 1.17.6. Stage 3: Write Calibration Part Two—DQ/DQS Centering 1.17.7. Stage 4: Read Calibration Part Two—Read Latency Minimization 1.17.8. Calibration Signals 1.17.9. Calibration Time

1.17.4. Stage 1: Read Calibration Part One—DQS Enable Calibration and DQ/DQS Centering

1.17.4.1. Guaranteed Write 1.17.4.2. DQS Enable Calibration 1.17.4.3. Centering DQ/DQS

2. Functional Description— Intel® Stratix® 10 EMIF IP

2.1. Stratix® 10 Supported Memory Protocols 2.2. Stratix® 10 EMIF IP Support for 3DS/TSV DDR4 Devices 2.3. Migrating to Stratix® 10 from Previous Device Families 2.4. Stratix® 10 EMIF Architecture: Introduction 2.5. Hardware Resource Sharing Among Multiple Stratix® 10 EMIFs 2.6. Stratix® 10 EMIF IP Component 2.7. Examples of External Memory Interface Implementations for DDR4 2.8. Stratix® 10 EMIF Sequencer 2.9. Stratix® 10 EMIF Calibration 2.10. Stratix 10 EMIF and SmartVID 2.11. Stratix® 10 Hard Memory Controller Rate Conversion Feature 2.12. Differences Between User-Requested Reset in Stratix® 10 versus Arria® 10 2.13. Compiling Stratix® 10 EMIF IP with the Quartus Prime Software 2.14. Debugging Stratix® 10 EMIF IP 2.15. Stratix® 10 EMIF for Hard Processor Subsystem 2.16. Stratix® 10 EMIF Ping Pong PHY 2.17. AFI 4.0 Specification 2.18. Stratix® 10 Resource Utilization 2.19. Stratix® 10 EMIF Latency 2.20. Integrating a Custom Controller with the Hard PHY 2.21. Document Revision History

2.4. Stratix® 10 EMIF Architecture: Introduction

2.4.1. Stratix® 10 EMIF Architecture: I/O Subsystem 2.4.2. Stratix® 10 EMIF Architecture: I/O Column 2.4.3. Stratix® 10 EMIF Architecture: I/O SSM 2.4.4. Stratix® 10 EMIF Architecture: I/O Bank 2.4.5. Stratix® 10 EMIF Architecture: I/O Lane 2.4.6. Stratix® 10 EMIF Architecture: Input DQS Clock Tree 2.4.7. Stratix® 10 EMIF Architecture: PHY Clock Tree 2.4.8. Stratix® 10 EMIF Architecture: PLL Reference Clock Networks 2.4.9. Stratix® 10 EMIF Architecture: Clock Phase Alignment

2.5. Hardware Resource Sharing Among Multiple Stratix® 10 EMIFs

2.5.1. I/O SSM Sharing 2.5.2. I/O Bank Sharing 2.5.3. PLL Reference Clock Sharing 2.5.4. Core Clock Network Sharing

2.6. Stratix® 10 EMIF IP Component

2.6.1. Instantiating Your Stratix® 10 EMIF IP in a Qsys Project 2.6.2. File Sets 2.6.3. Customized readme.txt File 2.6.4. Clock Domains 2.6.5. ECC in Stratix® 10 EMIF IP

2.6.1. Instantiating Your Stratix® 10 EMIF IP in a Qsys Project

2.6.1.1. Logical Connections

2.6.5. ECC in Stratix® 10 EMIF IP

2.6.5.1. ECC Components 2.6.5.2. ECC User Interface Controls

2.8. Stratix® 10 EMIF Sequencer

2.8.1. Stratix® 10 EMIF DQS Tracking

2.9. Stratix® 10 EMIF Calibration

2.9.1. Stratix® 10 Calibration Stages 2.9.2. Stratix® 10 Calibration Stages Descriptions 2.9.3. Stratix® 10 Calibration Algorithms 2.9.4. Stratix® 10 Calibration Flowchart

2.12. Differences Between User-Requested Reset in Stratix® 10 versus Arria® 10

2.12.1. Method for Initiating a User-requested Reset

2.13. Compiling Stratix® 10 EMIF IP with the Quartus Prime Software

2.13.1. Instantiating the Stratix® 10 EMIF IP 2.13.2. Setting I/O Assignments in Stratix® 10 EMIF IP

2.14. Debugging Stratix® 10 EMIF IP

2.14.1. External Memory Interface Debug Toolkit 2.14.2. On-Chip Debug for Stratix® 10 2.14.3. Configuring Your EMIF IP for Use with the Debug Toolkit 2.14.4. Stratix® 10 EMIF Debugging Examples

2.15. Stratix® 10 EMIF for Hard Processor Subsystem

2.15.1. Restrictions on I/O Bank Usage for Stratix® 10 EMIF IP with HPS

2.16. Stratix® 10 EMIF Ping Pong PHY

2.16.1. Stratix® 10 Ping Pong PHY Feature Description 2.16.2. Stratix® 10 Ping Pong PHY Architecture 2.16.3. Stratix® 10 Ping Pong PHY Limitations 2.16.4. Stratix® 10 Ping Pong PHY Calibration 2.16.5. Using the Ping Pong PHY 2.16.6. Ping Pong PHY Simulation Example Design

2.17. AFI 4.0 Specification

2.17.1. Bus Width and AFI Ratio 2.17.2. AFI Parameters 2.17.3. AFI Signals 2.17.4. AFI 4.0 Timing Diagrams

2.17.3. AFI Signals

2.17.3.1. AFI Clock and Reset Signals 2.17.3.2. AFI Address and Command Signals 2.17.3.3. AFI Write Data Signals 2.17.3.4. AFI Read Data Signals 2.17.3.5. AFI Calibration Status Signals 2.17.3.6. AFI Tracking Management Signals 2.17.3.7. AFI Shadow Register Management Signals

2.17.4. AFI 4.0 Timing Diagrams

2.17.4.1. AFI Address and Command Timing Diagrams 2.17.4.2. AFI Write Sequence Timing Diagrams 2.17.4.3. AFI Read Sequence Timing Diagrams 2.17.4.4. AFI Calibration Status Timing Diagram

2.18. Stratix® 10 Resource Utilization

2.18.1. QDR-IV Resource Utilization in Stratix® 10 Devices

3. Functional Description— Intel® Arria® 10 EMIF IP

3.1. Supported Memory Protocols 3.2. Key Differences Compared to UniPHY IP and Previous Device Families 3.3. Migrating from Previous Device Families 3.4. Arria® 10 EMIF Architecture: Introduction 3.5. Hardware Resource Sharing Among Multiple EMIFs 3.6. Arria® 10 EMIF IP Component 3.7. Examples of External Memory Interface Implementations for DDR4 3.8. Arria® 10 EMIF Sequencer 3.9. Arria® 10 EMIF Calibration 3.10. Back-to-Back User-Controlled Refresh Usage in Arria® 10 3.11. Arria® 10 EMIF and SmartVID 3.12. Hard Memory Controller Rate Conversion Feature 3.13. Back-to-Back User-Controlled Refresh for Hard Memory Controller 3.14. Compiling Arria® 10 EMIF IP with the Quartus Prime Software 3.15. Debugging Arria® 10 EMIF IP 3.16. Arria® 10 EMIF for Hard Processor Subsystem 3.17. Arria® 10 EMIF Ping Pong PHY 3.18. AFI 4.0 Specification 3.19. Resource Utilization 3.20. Arria® 10 EMIF Latency 3.21. Arria® 10 EMIF Calibration Times 3.22. Integrating a Custom Controller with the Hard PHY 3.23. Memory Mapped Register (MMR) Tables 3.247.7. Document Revision History3.247.7. Document Revision History

3.4. Arria® 10 EMIF Architecture: Introduction

3.4.1. Arria® 10 EMIF Architecture: I/O Subsystem 3.4.2. Arria® 10 EMIF Architecture: I/O Column 3.4.3. Arria® 10 EMIF Architecture: I/O AUX 3.4.4. Arria® 10 EMIF Architecture: I/O Bank 3.4.5. Arria® 10 EMIF Architecture: I/O Lane 3.4.6. Arria® 10 EMIF Architecture: Input DQS Clock Tree 3.4.7. Arria® 10 EMIF Architecture: PHY Clock Tree 3.4.8. Arria® 10 EMIF Architecture: PLL Reference Clock Networks 3.4.9. Arria® 10 EMIF Architecture: Clock Phase Alignment

3.4.4. Arria® 10 EMIF Architecture: I/O Bank

3.4.4.1. Implementing a x8 Interface with Hard Memory Controller 3.4.4.2. Implementing a x72 Interface with Hard Memory Controller

3.5. Hardware Resource Sharing Among Multiple EMIFs

3.5.1. I/O Aux Sharing 3.5.2. I/O Bank Sharing 3.5.3. PLL Reference Clock Sharing 3.5.4. Core Clock Network Sharing

3.6. Arria® 10 EMIF IP Component

3.6.1. Instantiating Your Arria® 10 EMIF IP in a Qsys Project 3.6.2. File Sets 3.6.3. Customized readme.txt File 3.6.4. Clock Domains 3.6.5. ECC in Arria® 10 EMIF IP

3.6.1. Instantiating Your Arria® 10 EMIF IP in a Qsys Project

3.6.1.1. Logical Connections

3.6.5. ECC in Arria® 10 EMIF IP

3.6.5.1. ECC Components 3.6.5.2. ECC User Interface Controls

3.8. Arria® 10 EMIF Sequencer

3.8.1. Arria® 10 EMIF DQS Tracking

3.9. Arria® 10 EMIF Calibration

3.9.1. Calibration Stages 3.9.2. Calibration Stages Descriptions 3.9.3. Calibration Algorithms 3.9.4. Calibration Flowchart 3.9.5. Periodic OCT Recalibration

3.9.5. Periodic OCT Recalibration

3.9.5.1. Operation 3.9.5.2. Technical Restrictions 3.9.5.3. Efficiency Impact

3.14. Compiling Arria® 10 EMIF IP with the Quartus Prime Software

3.14.1. Instantiating the Arria® 10 EMIF IP 3.14.2. Setting I/O Assignments in Arria® 10 EMIF IP

3.15. Debugging Arria® 10 EMIF IP

3.15.1. External Memory Interface Debug Toolkit 3.15.2. On-Chip Debug for Arria® 10 3.15.3. Configuring Your EMIF IP for Use with the Debug Toolkit 3.15.4. Arria® 10 EMIF Debugging Examples

3.16. Arria® 10 EMIF for Hard Processor Subsystem

3.16.1. Restrictions on I/O Bank Usage for Arria® 10 EMIF IP with HPS 3.16.2. Using the EMIF Debug Toolkit with Arria® 10 HPS Interfaces

3.17. Arria® 10 EMIF Ping Pong PHY

3.17.1. Ping Pong PHY Feature Description 3.17.2. Ping Pong PHY Architecture 3.17.3. Ping Pong PHY Limitations 3.17.4. Ping Pong PHY Calibration 3.17.5. Using the Ping Pong PHY 3.17.6. Ping Pong PHY Simulation Example Design

3.18. AFI 4.0 Specification

3.18.1. Bus Width and AFI Ratio 3.18.2. AFI Parameters 3.18.3. AFI Signals 3.18.4. AFI 4.0 Timing Diagrams

3.18.3. AFI Signals

3.18.3.1. AFI Clock and Reset Signals 3.18.3.2. AFI Address and Command Signals 3.18.3.3. AFI Write Data Signals 3.18.3.4. AFI Read Data Signals 3.18.3.5. AFI Calibration Status Signals 3.18.3.6. AFI Tracking Management Signals 3.18.3.7. AFI Shadow Register Management Signals

3.18.4. AFI 4.0 Timing Diagrams

3.18.4.1. AFI Address and Command Timing Diagrams 3.18.4.2. AFI Write Sequence Timing Diagrams 3.18.4.3. AFI Read Sequence Timing Diagrams 3.18.4.4. AFI Calibration Status Timing Diagram

3.19. Resource Utilization

3.19.1. QDR-IV Resource Utilization in Arria® 10 Devices

3.23. Memory Mapped Register (MMR) Tables

3.23.1. ctrlcfg0: Controller Configuration 3.23.2. ctrlcfg1: Controller Configuration 3.23.3. ctrlcfg2: Controller Configuration 3.23.4. ctrlcfg3: Controller Configuration 3.23.5. ctrlcfg4: Controller Configuration 3.23.6. ctrlcfg5: Controller Configuration 3.23.7. ctrlcfg6: Controller Configuration 3.23.8. ctrlcfg7: Controller Configuration 3.23.9. ctrlcfg8: Controller Configuration 3.23.10. ctrlcfg9: Controller Configuration 3.23.11. dramtiming0: Timing Parameters 3.23.12. dramodt0: On-Die Termination Parameters 3.23.13. dramodt1: On-Die Termination Parameters 3.23.14. sbcfg0: Sideband Configuration 3.23.15. sbcfg1: Sideband Configuration 3.23.16. sbcfg2: Sideband Configuration 3.23.17. sbcfg3: Sideband Configuration 3.23.18. sbcfg4: Sideband Configuration 3.23.19. sbcfg5: Sideband Configuration 3.23.20. sbcfg6: Sideband Configuration 3.23.21. sbcfg7: Sideband Configuration 3.23.22. sbcfg8: Sideband Configuration 3.23.23. sbcfg9: Sideband Configuration 3.23.24. caltiming0: Command/Address/Latency Parameters 3.23.25. caltiming1: Command/Address/Latency Parameters 3.23.26. caltiming2: Command/Address/Latency Parameters 3.23.27. caltiming3: Command/Address/Latency Parameters 3.23.28. caltiming4: Command/Address/Latency Parameters 3.23.29. caltiming5: Command/Address/Latency Parameters 3.23.30. caltiming6: Command/Address/Latency Parameters 3.23.31. caltiming7: Command/Address/Latency Parameters 3.23.32. caltiming8: Command/Address/Latency Parameters 3.23.33. caltiming9: Command/Address/Latency Parameters 3.23.34. caltiming10: Command/Address/Latency Parameters 3.23.35. dramaddrw: Row/Column/Bank Address Width Configuration 3.23.36. sideband0: Sideband address=43(32 bit) 3.23.37. sideband1: Sideband 3.23.38. sideband2: Sideband 3.23.39. sideband3: Sideband 3.23.40. sideband4: Sideband 3.23.41. sideband5: Sideband 3.23.42. sideband6: Sideband 3.23.43. sideband7: Sideband 3.23.44. sideband8: Sideband 3.23.45. sideband9: Sideband 3.23.46. sideband10: Sideband 3.23.47. sideband11: Sideband 3.23.48. sideband12: Sideband 3.23.49. sideband13: Sideband 3.23.50. sideband14: Sideband 3.23.51. sideband15: Sideband 3.23.52. dramsts: Calibration Status 3.23.53. ecc1: ECC General Configuration 3.23.54. ecc2: Width Configuration 3.23.55. ecc3: ECC Error and Interrupt Configuration 3.23.56. ecc4: Status and Error Information 3.23.57. ecc5: Address of Most Recent SBE/DBE 3.23.58. ecc6: Address of Most Recent Correct Command Dropped

4. Functional Description— Intel® MAX® 10 EMIF IP

4.1. MAX® 10 EMIF Overview 4.2. External Memory Protocol Support 4.3. MAX® 10 Memory Controller 4.4. MAX® 10 Low Power Feature 4.5. MAX® 10 Memory PHY 4.6. Calibration 4.7. Sequencer Debug Information 4.8. Register Maps 4.9. Document Revision History

4.5. MAX® 10 Memory PHY

4.5.1. Supported Topologies 4.5.2. Read Datapath 4.5.3. Write Datapath 4.5.4. Address and Command Datapath 4.5.5. Sequencer

4.6. Calibration

4.6.1. Read Calibration 4.6.2. Write Calibration

5. Functional Description—Hard Memory Interface

5.1. Multi-Port Front End (MPFE) 5.2. Multi-port Scheduling 5.3. MPFE Signal Descriptions 5.4. Hard Memory Controller 5.5. Hard PHY 5.6. Document Revision History

5.2. Multi-port Scheduling

5.2.1. Port Scheduling 5.2.2. DRAM Burst Scheduling 5.2.3. DRAM Power Saving Modes

5.4. Hard Memory Controller

5.4.1. Clocking 5.4.2. Reset 5.4.3. DRAM Interface 5.4.4. ECC 5.4.5. Bonding of Memory Controllers

5.5. Hard PHY

5.5.1. Interconnections 5.5.2. Clock Domains 5.5.3. Hard Sequencer 5.5.4. MPFE Setup Guidelines 5.5.5. Soft Memory Interface to Hard Memory Interface Migration Guidelines 5.5.6. Bonding Interface Guidelines

6. Functional Description—HPS Memory Controller

6.1. Features of the SDRAM Controller Subsystem 6.2. SDRAM Controller Subsystem Block Diagram 6.3. SDRAM Controller Memory Options 6.4. SDRAM Controller Subsystem Interfaces 6.5. Memory Controller Architecture 6.6. Functional Description of the SDRAM Controller Subsystem 6.7. SDRAM Power Management 6.8. DDR PHY 6.9. Clocks 6.10. Resets 6.11. Port Mappings 6.12. Initialization 6.13. SDRAM Controller Subsystem Programming Model 6.14. Debugging HPS SDRAM in the Preloader 6.15. SDRAM Controller Address Map and Register Definitions 6.16. Document Revision History

6.4. SDRAM Controller Subsystem Interfaces

6.4.1. MPU Subsystem Interface 6.4.2. L3 Interconnect Interface 6.4.3. CSR Interface 6.4.4. FPGA-to-HPS SDRAM Interface

6.5. Memory Controller Architecture

6.5.1. Multi-Port Front End 6.5.2. Single-Port Controller

6.5.2. Single-Port Controller

6.5.2.1. Command Generator 6.5.2.2. Timer Bank Pool 6.5.2.3. Arbiter 6.5.2.4. Rank Timer 6.5.2.5. Write Data Buffer 6.5.2.6. ECC Block 6.5.2.7. AFI Interface 6.5.2.8. CSR Interface

6.6. Functional Description of the SDRAM Controller Subsystem

6.6.1. MPFE Operation Ordering 6.6.2. MPFE Multi-Port Arbitration 6.6.3. MPFE SDRAM Burst Scheduling 6.6.4. Single-Port Controller Operation

6.6.4. Single-Port Controller Operation

6.6.4.1. Command and Data Reordering 6.6.4.2. Bank Policy 6.6.4.3. Write Combining 6.6.4.4. Burst Length Support 6.6.4.5. ECC 6.6.4.6. Interleaving Options 6.6.4.7. AXI-Exclusive Support 6.6.4.8. Memory Protection 6.6.4.9. Example of Configuration for TrustZone

6.6.4.5. ECC

6.6.4.5.1. Byte Writes 6.6.4.5.2. ECC Write Backs 6.6.4.5.3. User Notification of ECC Errors

6.10. Resets

6.10.1. Taking the SDRAM Controller Subsystem Out of Reset

6.12. Initialization

6.12.1. FPGA-to-SDRAM Protocol Details

6.12.1.1. Avalon-MM Bidirectional Port 6.12.1.2. Avalon-MM Write-Only Port 6.12.1.3. Avalon-MM Read Port 6.12.1.4. AXI Port

6.13. SDRAM Controller Subsystem Programming Model

6.13.1. HPS Memory Interface Architecture 6.13.2. HPS Memory Interface Configuration 6.13.3. HPS Memory Interface Simulation 6.13.4. Generating a Preloader Image for HPS with EMIF

6.13.4. Generating a Preloader Image for HPS with EMIF

6.13.4.1. Creating a Qsys Project 6.13.4.2. Creating a Top-Level File and Adding Constraints

6.14. Debugging HPS SDRAM in the Preloader

6.14.1. Enabling UART or Semihosting Printout 6.14.2. Enabling Simple Memory Test 6.14.3. Enabling the Debug Report 6.14.4. Writing a Predefined Data Pattern to SDRAM in the Preloader

6.14.3. Enabling the Debug Report

6.14.3.1. Analysis of Debug Report

7. Functional Description—HPC II Controller

7.1. HPC II Memory Interface Architecture 7.2. HPC II Memory Controller Architecture 7.3. HPC II Controller Features 7.4. External Interfaces 7.5. Top-Level Signals Description 7.6. Sequence of Operations 3.247.7. Document Revision History3.247.7. Document Revision History

7.2. HPC II Memory Controller Architecture

7.2.1. Backpressure Support 7.2.2. Command Generator 7.2.3. Timing Bank Pool 7.2.4. Arbiter 7.2.5. Rank Timer 7.2.6. Read Data Buffer and Write Data Buffer 7.2.7. ECC Block 7.2.8. AFI and CSR Interfaces

7.3. HPC II Controller Features

7.3.1. Data Reordering 7.3.2. Pre-emptive Bank Management 7.3.3. Quasi-1T and Quasi-2T 7.3.4. User Autoprecharge Commands 7.3.5. Address and Command Decoding Logic 7.3.6. Low-Power Logic 7.3.7. ODT Generation Logic 7.3.8. Burst Merging 7.3.9. ECC

7.3.9. ECC

7.3.9.1. Partial Writes 7.3.9.2. Partial Bursts

7.4. External Interfaces

7.4.1. Clock and Reset Interface 7.4.2. Avalon-ST Data Slave Interface 7.4.3. AXI Data Slave Interface 7.4.4. Controller-PHY Interface 7.4.5. Memory Side-Band Signals 7.4.6. Controller External Interfaces

7.4.3. AXI Data Slave Interface

7.4.3.1. Enabling the AXI Interface 7.4.3.2. AXI Interface Parameters 7.4.3.3. AXI Interface Ports

7.5. Top-Level Signals Description

7.5.1. Clock and Reset Signals 7.5.2. Local Interface Signals 7.5.3. Controller Interface Signals 7.5.4. CSR Interface Signals 7.5.5. Soft Controller Register Map 7.5.6. Hard Controller Register Map

8. Functional Description—QDR II Controller

8.1. Block Description 8.2. Avalon-MM and Memory Data Width 8.3. Signal Descriptions 8.4. Document Revision History

8.1. Block Description

8.1.1. Avalon-MM Slave Read and Write Interfaces 8.1.2. Command Issuing FSM 8.1.3. AFI

9. Functional Description—QDR-IV Controller

9.1. Block Description 9.2. Avalon-MM and Memory Data Width 9.3. Signal Descriptions 9.4. Document Revision History

9.1. Block Description

9.1.1. Avalon-MM Slave Read and Write Interfaces 9.1.2. AFI

10. Functional Description—RLDRAM II Controller

10.1. Block Description 10.2. User-Controlled Features 10.3. Avalon-MM and Memory Data Width 10.4. Signal Descriptions 10.5. Document Revision History

10.1. Block Description

10.1.1. Avalon-MM Slave Interface 10.1.2. Write Data FIFO Buffer 10.1.3. Command Issuing FSM 10.1.4. Refresh Timer 10.1.5. Timer Module 10.1.6. AFI

10.2. User-Controlled Features

10.2.1. Error Detection Parity 10.2.2. User-Controlled Refresh

11. Functional Description—RLDRAM 3 PHY-Only IP

11.1. Block Description 11.2. Features 11.3. RLDRAM 3 AFI Protocol 11.4. RLDRAM 3 Controller with Arria 10 EMIF Interfaces 11.5. Document Revision History

12. Functional Description—Example Designs

12.1. Arria 10 EMIF IP Example Designs Quick Start Guide 12.2. Testing the EMIF Interface Using the Traffic Generator 2.0 12.3. UniPHY-Based Example Designs 12.4. Document Revision History

12.1. Arria 10 EMIF IP Example Designs Quick Start Guide

12.1.1. Typical Example Design Workflow 12.1.2. Example Designs Interface Tab 12.1.3. Development Kit Preset Workflow 12.1.4. Compiling and Simulating the Design 12.1.5. Compiling and Testing the Design in Hardware

12.2. Testing the EMIF Interface Using the Traffic Generator 2.0

12.2.1. Configurable Traffic Generator 2.0 Configuration Options 12.2.2. Performing Your Own Tests Using Traffic Generator 2.0 12.2.3. Signal Splitter Component

12.2.1. Configurable Traffic Generator 2.0 Configuration Options

12.2.1.1. Test Information

12.3. UniPHY-Based Example Designs

12.3.1. Synthesis Example Design 12.3.2. Simulation Example Design 12.3.3. Traffic Generator and BIST Engine 12.3.4. Creating and Connecting the UniPHY Memory Interface and the Traffic Generator in Qsys

12.3.3. Traffic Generator and BIST Engine

12.3.3.1. Read and Write Generation 12.3.3.2. Address and Burst Length Generation 12.3.3.3. Traffic Generator Signals 12.3.3.4. Traffic Generator Add-Ons 12.3.3.5. Traffic Generator Timeout Counter

12.3.4. Creating and Connecting the UniPHY Memory Interface and the Traffic Generator in Qsys

12.3.4.1. Notes on Configuring UniPHY IP in Qsys

13. Introduction to UniPHY IP

13.1. Release Information 13.2. Device Support Levels 13.3. Device Family and Protocol Support 13.4. UniPHY-Based External Memory Interface Features 13.5. System Requirements 13.6. Intel® FPGA IP Core Verification 13.7. Resource Utilization 13.8. Document Revision History

13.7. Resource Utilization

13.7.1. DDR2, DDR3, and LPDDR2 Resource Utilization in Arria V Devices 13.7.2. DDR2 and DDR3 Resource Utilization in Arria II GZ Devices 13.7.3. DDR2 and DDR3 Resource Utilization in Stratix III Devices 13.7.4. DDR2 and DDR3 Resource Utilization in Stratix IV Devices 13.7.5. DDR2 and DDR3 Resource Utilization in Arria V GZ and Stratix V Devices 13.7.6. QDR II and QDR II+ Resource Utilization in Arria V Devices 13.7.7. QDR II and QDR II+ Resource Utilization in Arria II GX Devices 13.7.8. QDR II and QDR II+ Resource Utilization in Arria II GZ, Arria V GZ, Stratix III, Stratix IV, and Stratix V Devices 13.7.9. RLDRAM II Resource Utilization in Arria V Devices 13.7.10. RLDRAM II Resource Utilization in Arria II GZ, Arria V GZ, Stratix III, Stratix IV, and Stratix V Devices

14. Latency for UniPHY IP

14.1. DDR2 SDRAM LATENCY 14.2. DDR3 SDRAM LATENCY 14.3. LPDDR2 SDRAM LATENCY 14.4. QDR II and QDR II+ SRAM Latency 14.5. RLDRAM II Latency 14.6. RLDRAM 3 Latency 14.7. Variable Controller Latency 14.8. Document Revision History

15. Timing Diagrams for UniPHY IP

15.1. DDR2 Timing Diagrams 15.2. DDR3 Timing Diagrams 15.3. QDR II and QDR II+ Timing Diagrams 15.4. RLDRAM II Timing Diagrams 15.5. LPDDR2 Timing Diagrams 15.6. RLDRAM 3 Timing Diagrams 15.7. Document Revision History

16. External Memory Interface Debug Toolkit

16.1. User Interface 16.2. Setup and Use 16.3. Operational Considerations 16.4. Troubleshooting 16.5. Debug Report for Arria V and Cyclone V SoC Devices 16.6. On-Chip Debug Port for UniPHY-based EMIF IP 16.7. On-Chip Debug Port for Arria 10 EMIF IP 16.8. Driver Margining for Arria 10 EMIF IP 16.9. Read Setting and Apply Setting Commands for Arria 10 EMIF IP 16.10. Traffic Generator 2.0 16.11. The Traffic Generator 2.0 Report 16.12. Example Tcl Script for Running the EMIF Debug Toolkit 16.13. Calibration Adjustment Delay Step Sizes for Arria 10 Devices 16.14. Using the EMIF Debug Toolkit with Arria® 10 HPS Interfaces 16.15. Document Revision History

16.1. User Interface

16.1.1. Communication 16.1.2. Calibration and Report Generation

16.2. Setup and Use

16.2.1. General Workflow 16.2.2. Linking the Project to a Device 16.2.3. Establishing Communication to Connections 16.2.4. Selecting an Active Interface 16.2.5. Reports

16.5. Debug Report for Arria V and Cyclone V SoC Devices

16.5.1. Enabling the Debug Report for Arria V and Cyclone V SoC Devices 16.5.2. Determining the Failing Calibration Stage for a Cyclone V or Arria V HPS SDRAM Controller

16.6. On-Chip Debug Port for UniPHY-based EMIF IP

16.6.1. Access Protocol 16.6.2. Command Codes Reference 16.6.3. Header Files 16.6.4. Generating IP With the Debug Port 16.6.5. Example C Code for Accessing Debug Data

16.7. On-Chip Debug Port for Arria 10 EMIF IP

16.7.1. Access Protocol 16.7.2. EMIF On-Chip Debug Port 16.7.3. On-Die Termination Calibration 16.7.4. Eye Diagram

16.8. Driver Margining for Arria 10 EMIF IP

16.8.1. Determining Margin

16.9. Read Setting and Apply Setting Commands for Arria 10 EMIF IP

16.9.1. Reading or Applying Calibration Settings

16.10. Traffic Generator 2.0

16.10.1. Configuring the Traffic Generator 2.0 16.10.2. Running the Traffic Generator 2.0 16.10.3. Understanding the Custom Traffic Generator User Interface 16.10.4. Applying the Traffic Generator 2.0

16.13. Calibration Adjustment Delay Step Sizes for Arria 10 Devices

16.13.1. Addressing 16.13.2. Output and Strobe Enable Minimum and Maximum Phase Settings

17. Upgrading to UniPHY-based Controllers from ALTMEMPHY-based Controllers

17.1. Generating Equivalent Design 17.2. Replacing the ALTMEMPHY Datapath with UniPHY Datapath 17.3. Resolving Port Name Differences 17.4. Creating OCT Signals 17.5. Running Pin Assignments Script 17.6. Removing Obsolete Files 17.7. Simulating your Design 17.8. Document Revision History