External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

3.23.55. ecc3: ECC Error and Interrupt Configuration

address=130(32 bit)

Field Bit High Bit Low Description Access
cfg_gen_sbe 0 0 A value of 1 enables the generate SBE feature. Generates a single bit error during the write process. Read/Write
cfg_gen_dbe 1 1 A value of 1 enables the generate DBE feature. Generates a double bit error during the write process. Read/Write
cfg_enable_intr 2 2 A value of 1 enables the interrupt feature. The interrupt signal notifies if an error condition occurs. The condition is configurable. Read/Write
cfg_mask_sbe_intr 3 3 A value of 1 masks the interrupt signal when SBE occurs. Read/Write
cfg_mask_dbe_intr 4 4 A value of 1 masks the interrupt signal when DBE occurs. Read/Write
cfg_mask_corr_dropped_intr 5 5 A value of 1 masks the interrupt signal when auto correction command can’t be scheduled, due to back-pressure (FIFO full). Read/Write
cfg_mask_hmi_intr 6 6 A value of 1 masks the interrupt signal when the hard memory interface asserts an interrupt signal via ctrl_ecc_user_interrupt_0 port. Read/Write
cfg_clr_intr 7 7 Writing a vale of 1 to this self-clearing bit clears the interrupt signal, error status, and address. Read/Write
Reserved 31 9    

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