External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

3.23.32. caltiming8: Command/Address/Latency Parameters

address=39(32 bit)

Field Bit High Bit Low Description Access
cfg_t_param_mrr_to_valid 3 0 Timing parameter for Mode Register Read to any valid command. Read/Write
cfg_t_param_mpr_to_valid 8 4 Timing parameter for Multi Purpose Register Read to any valid command. Read/Write
cfg_t_param_mps_exit_cs_to_cke 12 9 Timing parameter for exit Maximum Power Saving. Timing requirement for CS assertion vs CKE de-assertion. tMPX_S Read/Write
cfg_t_param_mps_exit_cke_to_cs 16 13 Timing parameter for exit Maximum Power Saving. Timing requirement for CKE de-assertion vs CS de-assertion. tMPX_LH Read/Write
cfg_t_param_rld3_multibank_ref_delay 19 17 RLD3 Refresh to Refresh Delay for all sequences. Read/Write
cfg_t_param_mmr_cmd_to_valid 27 20 MMR cmd to valid delay. Read/Write

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