Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

21.5.1.2. Slave-Transmitter Operation for a Single Byte

When another I2C master device on the bus addresses the I2C controller and requests data, the I2C controller acts as a slave-transmitter and the following steps occur: †

  1. The other I2C master device initiates an I2C transfer with an address that matches the slave address in the IC_SAR register of the I2C controller †
  2. The I2C controller acknowledges the sent address and recognizes the direction of the transfer to indicate that it is acting as a slave-transmitter. †
  3. The I2C controller asserts the RD_REQ interrupt (bit 5 of the IC_RAW_INTR_STAT register) and waits for software to respond. †

    If the RD_REQ interrupt has been masked, due to bit 5 of the IC_INTR_MASK register (M_RD_REQ bit field) being set to 0, then it is recommended that you instruct the CPU to perform periodic reads of the IC_RAW_INTR_STAT register. †

    • Reads that indicate bit 5 of the IC_RAW_INTR_STAT register (R_RD_REQ bit field) being set to 1 must be treated as the equivalent of the RD_REQ interrupt being asserted. †
    • Software must then act to satisfy the I2C transfer. †
    • The timing interval used should be in the order of 10 times the fastest SCL clock period the I2C controller can handle. For example, for 400 Kbps, the timing interval is 25 us. †
      Note: The value of 10 is recommended here because this is approximately the amount of time required for a single byte of data transferred on the I2C bus.†
  4. If there is any data remaining in the TX FIFO before receiving the read request, the I2C controller asserts a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register) to flush the old data from the TX FIFO. †
    Note: Because the I2C controller's TX FIFO is forced into a flushed/reset state whenever a TX_ABRT event occurs, it is necessary for software to release the I2C controller from this state by reading the IC_CLR_TX_ABRT register before attempting to write into the TX FIFO. For more information, refer to the C_RAW_INTR_STAT register description in the register map.†

    If the TX_ABRT interrupt has been masked, due to of IC_INTR_MASK[6] register (M_TX_ABRT bit field) being set to 0, then it is recommended that the CPU performs periodic reads of the IC_RAW_INTR_STAT register. †

    • Reads that indicate bit 6 (R_TX_ABRT) being set to 1 must be treated as the equivalent of the TX_ABRT interrupt being asserted. †
    • There is no further action required from software. †
    • The timing interval used should be similar to that described in the previous step for the IC_RAW_INTR_STAT[5] register. †
  5. Software writes to the DAT bits of the IC_DATA_CMD register with the data to be written and writes a 0 in bit 8.†
  6. Software must clear the RD_REQ and TX_ABRT interrupts (bits 5 and 6, respectively) of the IC_RAW_INTR_STAT register before proceeding. †

    If the RD_REQ or TX_ABRT interrupt is masked, then clearing of the IC_RAW_INTR_STAT register has already been performed when either the R_RD_REQ or R_TX_ABRT bit has been read as 1.

  7. The I2C controller transmits the byte. †
  8. The master may hold the I2C bus by issuing a RESTART condition or release the bus by issuing a STOP condition. †