Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

7.2.2.2.1.2. Non-secure Transaction Configuration

When the SoC is released from reset, only secure transactions are allowed through the firewalls. The user must configure any master-slave pairs that are required to be non-secure.

The SCR registers must be accessed in secure mode to configure the firewall access to non-secure.
  1. After the SoC is released from reset, the MPU, FPGA2SOC masters or the DAP accesses the required Security Configuration Register (SCR) by executing a secure write. The peripheral firewall SCR registers are within the soc_noc_fw_l4_per register group and the system firewall SCR registers are found within the soc_noc_fw_l4_sys register group.
  2. To configure the slave to allow a non-secure access by a master, set the corresponding security bit to 1.
The configured master is able to successfully execute a non-secure read or write to the configured slave.