Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

4.1.3. Module Reset Signals

The following tables list the module reset signals. The module reset signals are organized in groups for the MPU, peripherals, bridges.

In the following tables, columns marked for Cold Reset, Warm Reset, and Debug Reset denote reset signals asserted by each type of reset. For example, writing a 1 to the swwarmrstreq bit in the ctrl register resets all the modules that have a checkmark in the Warm Reset column.

Note: For warm resets, software can set the warmmask registers to prevent the assertion of module reset signals to peripheral modules.

The column marked for Software Deassert denotes reset signals that are left asserted by the reset manager.

Table 20.  MPU Group, Generated Module Resets

Module Reset Signal

Description

Reset Domain

Cold Reset

Warm Reset

Debug Reset

Software Deassert

mpu_cpu_rst_n[0] Resets each processor in the MPU System X X    
mpu_cpu_rst_n[1]

Resets each processor in the MPU

System

X X   X
mpu_wd_rst_n

Resets both per-processor watchdogs in the MPU

System

X X    
mpu_scu_periph_rst_n

Resets Snoop Control Unit (SCU) and peripherals

System

X X    
Table 21.  PER1 Group, Generated Module Resets

Module Reset Signal

Description

Reset Domain

Cold Reset

Warm Reset

Debug Reset

Software Deassert
watchdog_rst_n[1:0]

Resets corresponding system watchdog timer

System

X

X

  X
l4sys_timer_rst_n[1:0]

Resets corresponding OSC1 timer

System

X

X

  X
sp_timer_rst_n[1:0]

Resets corresponding SP timer

System

X

X

  X
i2c_rst_n[4:0]

Resets corresponding I2C controller

System

X

X

  X
uart_rst_n[1:0]

Resets corresponding UART

System

X

X

  X
gpio_rst_n[2:0]

Resets corresponding GPIO interface

System

X

X

  X
dma_periph_if_rst_n[7:0] DMA controller request interface from FPGA fabric to DMA controller System

X

X

 

X

emac_ptp_rst_n [1:0] Resets corresponding EMAC precision time protocol

System

X

X

   
emac_ecc_rst_n [2:0] Resets corresponding to EMAC ECC

System

X

X

   
usb_ecc_rst_n [1:0] Resets corresponding to USB ECC

System

X

X

   
nand_flash_ecc_rst_n Resets corresponding to NAND Flash ECC

System

X

X

   
qspi_flash_ecc_rst_n Resets corresponding to QSPI Flash ECC

System

X

X

   
sdmmc_ecc_rst_n Resets corresponding to SDMMC ECC

System

X

X

   
Table 22.  PER0 Group, Generated Module Resets

Module Reset Signal

Description

Reset Domain

Cold Reset

Warm Reset

Debug Reset

Software Deassert
emac_rst_n[2:0]

Resets corresponding EMAC

System

X

X

  X
usb_rst_n[1:0]

Resets corresponding USB

System

X

X

  X
nand_flash_rst_n

Resets NAND flash controller

System

X

X

  X
qspi_flash_rst_n

Resets quad SPI flash controller

System

X

X

  X
spim_rst_n[1:0]

Resets SPI master controller

System

X

X

  X
spis_rst_n[1:0]

Resets SPI slave controller

System

X

X

  X
sdmmc_rst_n

Resets SD/MMC controller

System

X

X

  X
dma_rst_n

Resets DMA controller

System

X

X

  X
dma_ecc_rst_n

Resets DMA ECC

System

X

X

   
Table 23.  Bridge Group, Generated Module Resets
Module Reset Signal Description Reset Domain Cold Reset Warm Reset Debug Reset Software Deassert
hps2fpga_bridge_rst_n Resets HPS-to-FPGA AMBA* Advanced eXtensible Interface ( AXI* ) bridge System X X   X
fpga2hps_bridge_rst_n Resets FPGA-to-HPS AXI* bridge System X X   X
lwhps2fpga_bridge_rst_n Resets lightweight HPS-to-FPGA AXI* bridge System X X   X
f2h_sdram_bridge0_rst_n Resets SDRAM bridge 0 System X X   X
f2h_sdram_bridge1_rst_n Resets SDRAM bridge 1 System X X   X
f2h_sdram_bridge2_rst_n Resets SDRAM bridge 2 System X X   X
ddr_scheduler_rst_n Resets DDR scheduler System X X   X
Table 24.  MISC Group, Generated Module Resets
Group Module Reset Signal Description Reset Domain Cold Reset Warm Reset Debug Reset Software Deassert
SYSMOD boot_rom_rst_n Resets boot ROM System X X    
onchip_ram_rst_nsy Resets on-chip RAM System X X    
sys_manager_rst_n Resets system manager (resets logic associated with cold or warm reset) System X      
fpga_manager_rst_n Resets FPGA manager System X X    
sys_dbg_rst_n Resets debug masters and slaves connected to L3 interconnect and level 4 (L4) buses System X X    
onchip_ram_ecc_rst_n Onchip RAM ECC reset System X X    
h2f_rst_n   System X X    
sec_rst_n Security reset System X      
COLD sys_manager_cold_rst_n Resets system manager (resets logic associated with cold reset only) System X      
rst_pin_oe_rst Pulls nRST pin low System X X    
timestamp_cold_rst_n Resets debug timestamp to 0x0 System X      
clk_manager_cold_rst_n Resets clock manager (resets logic associated with cold reset only) System X      
tap_cold_rst_n Resets portion of TAP controller in the DAP that must be reset on a cold reset TAP X      
sec_cold_rst_n Security cold reset System X      
hmc_cold_rst_n HMC cold reset System X X    
io_manager_cold_rst_n I/O manager cold reset System X X    
DBUG dbg_rst_n Resets debug components including DAP, trace, MPU debug logic, and any user debug logic in the FPGA fabric Debug X   X  
L3 l3_rst_n Resets L3 Interconnect and L4 buses System X X    
Table 25.  RAM Clear Group, Generated Module Resets
Module Reset Signal Reset Domain Cold Reset Warm Reset Debug Reset Software Deassert
onchip_sec_ram_rst_n X X X    
otg0_sec_ram_rst_n   X X    
otg1_sec_ram_rst_n   X X    
sdmmc_sec_ram_rst_n   X X    
emac0rx_sec_ram_rst_n   X X    
emac0tx_sec_ram_rst_n   X X    
emac1rx_sec_ram_rst_n   X X    
emac1tx_sec_ram_rst_n   X X    
emac2rx_sec_ram_rst_n   X X    
emac2tx_sec_ram_rst_n   X X    
dma_sec_ram_rst_n   X X    
nandw_sec_ram_rst_n   X X    
nandr_sec_ram_rst_n   X X    
nande_sec_ram_rst_n   X X    
qspi_sec_ram_rst_n   X X    
mwp_sec_ram_rst_n   X X    
Table 26.  L3 Group, Generated Module Resets
Module Reset Signal Description Reset Domain Cold Reset Warm Reset Debug Reset Software Deassert
misc Resets L3 interconnect and L4 buses System X X