Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 5/09/2025
Public

Visible to Intel only — GUID: sfo1410068293272

Ixiasoft

Document Table of Contents

10.3.1. Functional Description

The Arm* Cortex* -A9 MPCore contains the following sub-modules:

  • Two Cortex* -A9 Revision r4p1 processors operating in SMP or AMP mode
  • Snoop control unit (SCU)
  • Private interval timer for each processor core
  • Private watchdog timer for each processor core
  • Global timer
  • Interrupt controller

Each transaction originating from the Cortex* -A9 MPU subsystem can be flagged as secure or non-secure.