Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

21.4.3.3.2. Master-Receiver and Slave-Transmitter

If the master is receiving data as shown in the following figure, then the master responds to the slave-transmitter with an ACK pulse after a byte of data has been received, except for the last byte. This is the way the master-receiver notifies the slave-transmitter that this is the last byte. The slave-transmitter relinquishes the SDA line after detecting the No Acknowledge (NACK) bit so that the master can issue a STOP condition. †

When a master does not want to relinquish the bus with a STOP condition, the master can issue a RESTART condition. This is identical to a START condition except it occurs after the ACK pulse. Operating in master mode, the I2C controller can then communicate with the same slave using a transfer of a different direction. For a description of the combined format transactions that the I2C controller supports, refer to “Combined Formats” section of this chapter. †

Note: The I2C controller must be inactive on the serial port before the target slave address register, IC_TAR, can be reprogrammed. †
Figure 130. Master-Receiver Protocol †