Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

18.1.1. MAC

  • IEEE 802.3‑2008 compliant
  • Data rates of 10/100/1000 Mbps
  • Full duplex and half duplex modes
    • IEEE 802.3x flow control automatic transmission of zero-quanta pause frame on flow control input deassertion
    • Optional forwarding of received pause control frames to the user
    • Packet bursting and frame extension in 1000 Mbps half-duplex
    • IEEE 802.3x flow control in full-duplex
    • Back-pressure support for half-duplex
  • 4 KB TX FIFO RAM and 16 KB RX FIFO RAM with ECC support
  • IEEE 1588‑2002 and IEEE 1588‑2008 precision networked clock synchronization
  • IEEE 802.3‑az, version D2.0 for Energy Efficient Ethernet (EEE)
  • IEEE 802.1Q Virtual Local Area Network (VLAN) tag detection for reception frames
  • Preamble and start-of-frame data (SFD) insertion in transmit and deletion in receive paths
  • Automatic cyclic redundancy check (CRC) and pad generation controllable on a per-frame basis
  • Options for automatic pad/CRC stripping on receive frames
  • Programmable frame length supporting standard and jumbo Ethernet frames (with sizes up to 3800 bytes)
  • Programmable inter-frame gap (IFG), from 40- to 96-bit times in steps of eight bits
  • Preamble lengths of one, three, five and seven bytes supported
  • Supports internal loopback asynchronous FIFO on the GMII/MII for debugging
  • Supports a variety of flexible address filtering modes
    • Up to 31 additional 48-bit perfect destination address (DA) filters with masks for each byte
    • Up to 31 48-bit source address (SA) comparison check with masks for each byte
    • 256-bit hash filter (optional) for multicast and unicast DAs
    • Option to pass all multicast addressed frames
    • Promiscuous mode support to pass all frames without any filtering for network monitoring
    • Passes all incoming packets (as per filter) with a status report