Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

8.2.5.2. List of SDRAM L3 Interconnect Clocks

Table 51.  SDRAM L3 Interconnect Clocks
Clock Name Description Synchronous to l3_main_free_clk
hmc_free_clk

Clock from the hard memory controller. Clocks the SDRAM L3 interconnect. The hmc_free_clk frequency is ½ the interface clock frequency.

N

f2s_sdram_clk [2:0]

Clocks the FPGA-to-SDRAM interfaces.

N