Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

10.3.14. Snoop Control Unit

The SCU manages data traffic for the Cortex*-A9 processors and the memory system, including the L2 cache. In a multi‑master system, the processors and other masters can operate on shared data. The SCU ensures that each processor operates on the most up‑to‑date copy of data, maintaining cache coherency.