Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

16.4.12. Clocks

There are two clock inputs to the quad SPI controller: l4_mp_clk and l4_main_clk; and one clock output: qspi_clk. The quad SPI flash controller uses the l4_mp_clk clock to clock the data slave transfers and register slave accesses. The l4_main_clk clock is the reference clock for the quad SPI controller and is used to serialize the data and drive the external SPI interface. The qspi_clk clock is the generated clock source for the connected flash devices.

The following is true for the following reference clocks:
  • l4_main_clk should be greater than l4_mp_clk
  • l4_main_clk must be greater than two times qspi_clk

The qspi_clk clock is derived by dividing down the reference clock, l4_main_clk clock by the baud rate divisor field (bauddiv) of the cfg register.