Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

3.2.2. Boot Clock

The Boot Clock (boot_clk) is used as the default clock for both cold or warm reset (Boot Mode), the Hardware Sequencer local clock and the external bypass clock reference.

The boot_clk is generated from the secure cb_intosc_hs_div2_clk or the unsecure external oscillator. boot_clk is only updated coming out of cold reset or a warm reset (boot mode request) and is not sampled at any other time.

The source of every output clock block comes from the following:

  • Bypass source: boot_clock configured through fuses and security manager: registers at cold or warm reset
  • Non-External Bypass: Each Clock may come from 1 of 5 sources:
Table 12.  Non-External Bypass Sources of clocks
Source Description
OSC1 Pin for external oscillator
f2h_free_clk FPGA fabric PLL clock reference
cb_intosc_hs_div2_clk FPGA CSS (Control Block) high speed internal oscillator divided by 2 (200 MHz maximum)
PLL0 Counter Output Main PLL counter outputs 0 to 8
PLL1 Counter Output Peripheral PLL counter outputs 0 to 8

Clock Output Blocks have the following features:

  • Each clock output block contains an external bypass multiplexer
  • Some clock output blocks contain additional dividers
  • Clock gates controlled by either hardware or software are used to disable the clocks
  • The MPU and NOC (includes debug clocks) blocks contain enable outputs to define clock frequency ratios to the MPU, NOC and CoreSight logic

The CSR Register logic uses an independent clock, l4_sys_free_clk, to allow the clock to be changed by software.