Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

29.2.5. Peripheral FPGA Clocks

Table 239.  Peripheral FPGA Clocks

Clock Name

Description

emac_md_clk

Ethernet PHY management interface clock

emac_gtx_clk

Ethernet transmit clock that is used by the PHY in GMII mode

emac_rx_clk_in

Ethernet MAC reference clock from the PHY

emac_tx_clk_in

Ethernet MAC uses this clock input for TX reference

emac_ptp_ref_clock

Ethernet timestamp precision time protocol (PTP) reference clock

qspi_sclk_out

QSPI master clock output

qspi_s2f_clk

QSPI serial clock output (connects to the FPGA clock network)

sdmmc_clk_in

Clock for SD/MMC controller

sdmmc_cclk

Generated output clock for card

spim_sclk_out

SPI master serial clock output

spis_sclk_in

SPI slave serial clock input

i2c_clk

I2C outgoing clock (part of the SCL bidirectional pin signals)

i2c_scl_in

I2C incoming clock (part of the SCL bidirectional pin signals)

i2cemac_clk I2C EMAC outgoing clock
Note: The Peripheral FPGA Clocks can only be accessed once the corresponding IP Block has been selected and routed to the FPGA through the Pin Mux and Peripherals tab.