Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

14.1. NAND Flash Controller Features

The NAND flash controller provides the following functionality and features:
  • Supports one x8 or x16 NAND flash device
    Note: The HPS supports booting only from a x8 NAND flash device.
  • Supports Open NAND Flash Interface (ONFI) 1.0
  • Supports NAND flash memories from Hynix, Samsung, Toshiba, Micron, and STMicroelectronics
  • Supports error correction codes (ECCs) providing single-bit error correction and double-bit error detection, with:
    • Sector size programmable 512 byte (4-, 8-, or 16-bit correction) or 1024 byte (24-bit correction)
    • Three NAND FIFOs - ECC Buffer, write FIFO and read FIFO
  • Supports pipeline read‑ahead and write commands for enhanced read and write throughput
  • Supports devices with 32, 64, 128, 256, 384, or 512 pages per block
  • Supports multiplane devices
  • Supports page sizes of 512 bytes, 2 kilobytes (KB), 4 KB, or 8 KB
  • Supports single layer cell (SLC) and multiple layer cell (MLC) devices with programmable correction capabilities
  • Provides internal direct memory access (DMA)
  • Provides programmable access timing