Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

3.3.7. Security

The clock manager creates a boot clock as the clock reference for boot mode and external bypass. The clock configuration is based on security features in the security manager.

Security Input Clocks

The following table defines the boot clock sources.

Table 16.  Security Input Clocks
Clock Name Max Min Source/Dest Description
HPS_CLK1 50 10 Pin External Oscillator Clock Reference. Non-secure clock reference. Named osc1_clk signal inside device.
cb_intosc_hs_clk 400 120 FPGA Control Block

Control Block high speed internal ring oscillator. This clock has wide variation across process/temperature.

This clock is used as the secure reference for Boot Mode. Because the range/jitter of the clock is low quality, the clock is divided by 2.

cb_intosc_ls_clk 100 30 FPGA Control Block

Control Block low speed internal ring oscillator. This clock has wide variation across process/temperature.

This clock is used by Security Manager as the Power on Reset Domain secure clock.

This clock is also provided as an input to the Clock Manager PLLs. However, because of the low quality of the clock, it is not recommended to use this clock as the PLL reference.

Boot Clock

The status of the hps_clk_f security fuse in the Security Manager determines if boot_clk should be secure:

  • If set, then boot_clk is cb_intosc_hs_clk divided by 2.
  • If clear, then boot_clk comes from the external oscillator input pin HPS_CLK1.

The above setting is reported by the security manager before the chip is brought out of cold reset. Also the security status may be updated by security option registers in the security manager.