Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

21.4.2.1. START and STOP Generation

When operating as a master, putting data into the transmit FIFO causes the I2C controller to generate a START condition on the I2C bus. In order for the master to complete the transfer and issue a STOP condition it must find a transmit FIFO entry tagged with a stop bit. Allowing the transmit FIFO to empty without a stop bit set, the master will stall the transfer by holding the SCL line low. †

When operating as a slave, the I2C controller does not generate START and STOP conditions, as per the protocol. However, if a read request is made to the I2C controller, it holds the SCL line low until read data has been supplied to it. This stalls the I2C bus until read data is provided to the slave I2C controller, or the I2C controller slave is disabled by writing a 0 to bit 0 of IC_ENABLE register. †