Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

29.5.1.2. SD/MMC Controller Interface

Table 241.  SD/MMC Controller Interface Platform Designer (Standard) Port Mappings
Platform Designer (Standard) Port Name Routed to FPGA Routed to HPS I/O HPS Pin Name
sdmmc_vs_o Yes No -
sdmmc_pwr_ena_o Yes Yes SDMMC_PWR_ENA
sdmmc_wp_i Yes No -
sdmmc_cdn_i Yes No -
sdmmc_rstn_o Yes No -
sdmmc_card_intn_i Yes No -
sdmmc_clk_in_i Yes No -
sdmmc_cclk_out Yes Yes SDMMC_CCLK
sdmmc_cmd_i Yes Yes SDMMC_CMD
sdmmc_cmd_o Yes Yes
sdmmc_cmd_oe Yes Yes
sdmmc_data_i[7:0] Yes Yes SDMMC_DATA[7:0]
sdmmc_data_o[7:0] Yes Yes
sdmmc_data_oe Yes Yes