Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

8.2.5.1. List of Main L3 Interconnect Clocks

Table 50.  Main L3 Interconnect Clocks

Clock Name

Description

Synchronous to l3_main_free_clk

l3_main_free_clk

Clocks the main L3 interconnect

l4_sys_free_clk

Clocks the following interconnect components:

  • The L4 system bus
  • The interface to the DAP

Y

l4_main_clk

Clocks fast L4 peripherals on the L4 main bus

Refer to "System Interconnect Master Properties" and "System Interconnect Slave Properties" for detailed peripheral-to-clock mappings.

Y

l4_mp_clk

Clocks the following interconnect components:

  • Mid-speed L4 peripherals on the L4 MP bus
  • The L4 AHB* bus
  • The L4 ECC bus

Refer to "System Interconnect Master Properties" and "System Interconnect Slave Properties" for detailed peripheral-to-clock mappings.

Y

l4_sp_clk

Clocks slow L4 peripherals on the L4 SP bus. Refer to "System Interconnect Master Properties" and "System Interconnect Slave Properties" for detailed peripheral-to-clock mappings.

Y

cs_at_clk

CoreSight* trace clock. Clocks the CoreSight* Embedded Trace Router (ETR) master interface.

Y

mpu_l2ram_clk

Clocks the MPU subsystem master interfaces.

N

fpga2hps_clk

Clocks the FPGA-to-HPS bridge.

N

hps2fpga_clk

Clocks the HPS-to-FPGA bridge.

N

lwh2fpga_clk

Clocks the lightweight HPS-to-FPGA bridge.

N