Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

12.4.2. ECC Structure

The ECC is calculated based on a Hamming code for the corresponding data word length.

Table 111.  ECC Bits Required Based on Data Width
Data Bus Width ECC Bits
8 to 15 bits 5
16 to 31 bits 6
32 to 63 bits 7
64 to 127 bits 8
128 to 255 bits 9
256 bits 10
Table 112.  ECC Memory Characteristics

This table shows the memory data size and the Hamming code word length for each of the ECC-protected memories in the HPS, as well as the memory type. The Hamming code word length is calculated based on the full data width and whether the memory is byte- or word- addressable.

Notice that the on-chip RAM and DMA are byte-addressable. For each byte of data, five syndrome bits are used. For a data size of 64 bits (8 bytes), a total of 8 bytes*(8-bit data + 5-bit ECC) bits are used for a Hamming code word.

Peripheral Memory

Data Size

Memory

ECC Bits Data Width + ECC Bits

Hamming Code Word (length in bits)

Type 23

On-chip RAM

64 x 32768

Byte-addressable 5 per byte lane 64+40 24

104

Single port

USB RAM

35 x 8192

Word-addressable 7 35+7

42

Single port

SD/MMC FIFO

32 x 1024

Word-addressable 7 32+7

39

True dual port

EMAC Rx FIFO

35 x 4096

Word-addressable 7 35+7

42

Simple dual port

EMAC Tx FIFO

35 x 1024

Word-addressable 7 35+7

42

Simple dual port

DMA FIFO

64 x 512

Byte-addressable 5 per byte lane 64+4024

104

Simple dual port

NAND ECC Buffer

16 x 768

Word-addressable 6 16+6

22

Simple dual port

NAND Write FIFO

32 x 128

Word-addressable 7 32+7

39

Simple dual port

NAND Read FIFO

32 x 32

Word-addressable 7 32+7

39

Simple dual port

QSPI RAM

32 x 128

Word-addressable 7 32+7

39

Single port

23 True dual-port memory has two writeable and two readable ports. Simple dual port memory has one write-only port and one read-only port.
24 This is the same as 8 byte lanes with 5 ECC bits per lane.