Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

4.2.1.3. Cold and Warm Reset Deassertion Sequence

The following list describes the deassertion steps for both cold and warm reset shown in the Cold Reset Timing Diagram and Warm Reset Timing Diagram:

  1. De-assert all RAM CLEAR resets. Reset Manager Initiates Clock Manager MPU clocks stop request.
  2. Clock manager stops the MPU clocks and then waits 16 MPU clocks.
  3. Clock manager asserts Clock stop acknowledge to Reset Manager.
  4. Reset manager sees acknowledge and de-asserts L2 (mpu_l2_rst_n) reset only. Reset Manager de-asserts MPU stop request.
  5. Clock manger sees request de-asserted. Wait 16 MPU clocks. Start MPU clocks, and Clock Manager de-asserts Clock stop acknowledge.
  6. Reset manager sees de-assertion of acknowledge. Wait 16 cycles.
  7. Reset manager asserts CPU0/1 CLKOFF signals and waits 32 cycles.
  8. Reset manager de-asserts CPU0, CPU1, and SCU MPU resets (not WD). Wait 32 additional cycles.
  9. De-assert CPU0/1 CLKOFF signals. Wait 16 cycles
  10. Reset manager checks the Security fuse setting, and if the appropriate cold or warm reset fuse is set, do full RAM clearing sequence. Otherwise, clear only the MPU L1 RAM.
  11. Wait for Security RAM Sequence to complete.
  12. Assert again the CPU0, CPU1 and SCU MPU resets. Wait 16 cycles.
  13. De-assert L3 reset, and if Cold Reset, de-assert DBG and COLD groups of resets. Wait for 100 cycles
  14. De-assert SYS group module resets. Wait for 200 cycles.
  15. Reset manager Initiates Clock Manager MPU clocks stop request.
  16. Clock manager stops the MPU clocks and then waits 16 MPU clocks.
  17. Clock manager asserts Clock stop acknowledge to Reset Manager.
  18. Reset manager sees acknowledge and de-asserts L2 (mpu_l2_rst_n) reset only. Reset Manager de-asserts MPU stop request.
  19. Clock manger sees request de-asserted. Wait 16 MPU clocks. Start MPU clocks, and Clock Manager de-asserts Clock stop acknowledge.
  20. Reset manager sees de-assertion of acknowledge. Wait 16 cycles.
  21. Reset manager asserts CPU0 CLKOFF signal(s) and waits 32 cycles.
  22. Reset manager de-asserts remaining CPU0, SCU, and WD resets (no CPU1). Wait 32 additional cycles.
  23. De-assert CPU0 CLKOFF signal(s). De-assertion sequence is finished.
  24. Now SW should start running. SW to de-assert FPER/PER/SPER/BRIDGE/MPU2 resets.