Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

26.3.4.4. FPGA Access MUX Registers

The FPGA access ("use FPGA") MUX registers select whether each HPS peripheral uses HPS I/O pins or is routed to the FPGA fabric.

All peripherals except the USBs can be routed to the FPGA. The following FPGA access registers are available:

  • pinmux_emac0_usefpga
  • pinmux_emac1_usefpga
  • pinmux_emac2_usefpga
  • pinmux_i2c0_usefpga
  • pinmux_i2c1_usefpga
  • pinmux_i2c_emac0_usefpga
  • pinmux_i2c_emac1_usefpga
  • pinmux_i2c_emac2_usefpga
  • pinmux_nand_usefpga
  • pinmux_qspi_usefpga
  • pinmux_sdmmc_usefpga
  • pinmux_spim0_usefpga
  • pinmux_spim1_usefpga
  • pinmux_spis0_usefpga
  • pinmux_spis1_usefpga
  • pinmux_uart0_usefpga
  • pinmux_uart1_usefpga

At cold reset, the FPGA access registers default to 0, selecting the HPS I/O pins. These registers are not affected by a warm reset event.

Note: Although the FPGA access MUX is configured through the control registers, Intel recommends against reconfiguring the FPGA access MUX after I/O configuration is complete.