Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

10.2.1. Cortex*-A9 MPU Subsystem with System Interconnect

This block diagram shows a dual‑core MPU subsystem in the context of the HPS, with the L2 cache. The L2 cache can access either the system interconnect or the SDRAM L3 Interconnect.

Figure 40.  Cortex*-A9 MPU Subsystem with Interconnect Block Diagram