Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

13.1.2. On-Chip RAM Block Diagram and System Integration

Figure 56. On-Chip RAM Block Diagram

The on-chip RAM and L3 interconnect transfers data through a 64-bit interface that passes through a firewall, operating at the l3_main_free_clk interconnect clock frequency. For memory, read acceptance is two, write acceptance is two, and total acceptance is two with a round-robin arbitration.