Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

8.1.5.1. Features of the SDRAM L3 Interconnect

The SDRAM L3 interconnect supports the following features:
  • Connectivity to the SDRAM hard memory controller supporting:
    • DDR4-SDRAM
    • DDR3-SDRAM
  • Integrated SDRAM scheduler, functioning as a multi-port front end (MPFE)
  • Configurable SDRAM device data widths
    • 16-bit, with or without 8-bit error-correcting code (ECC)
    • 32-bit, with or without 8-bit ECC
    • 64-bit, with or without 8-bit ECC
  • High-performance ports
    • MPU subsystem port
    • Main L3 interconnect port
    • Three FPGA ports
      • Two 32-, 64-, or 128-bit ports
      • One 32- or 64-bit port
    • Firewall and security support port
Note: At system startup, the SDRAM I/O pins can be configured separately from the FPGA fabric, allowing the SoC HPS to boot before any soft logic is configured in the FPGA.