Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

14.3. NAND Flash Controller Signal Descriptions

All NAND pins have to be from one of the following categories:
  • HPS Dedicated
  • Shared
  • FPGA
The following table lists all NAND Flash Interface signals available to both the HPS and FPGA.
Pins Supported Data Width Supported Number of CE and R/B
HPS Dedicated Pins x8 1
Shared Pins x8/x16 1
FPGA Pins x8/x16 1 – 4
The type of pins you use determines the number of Chip Enable (CE) and Ready/Busy (RB) pairs available to you for use. For example, if you use HPS dedicated pins or shared pins, you can only use one CE and R/B pair. If you use FPGA pins, you can use multiple CE and R/B pairs.
Note: The options are mutually exclusive, which means you cannot use HPS dedicated pins, and route the CE and R/B signals to FPGA dedicated pins.
For more information on which signals route to the FPGA and HPS I/O, please refer to the HPS Component Interface chapter.
Table 118.  NAND Flash Interface Signals
Platform Designer (Standard) Port Name Connected to FPGA Connected to HPS I/O HPS Pin Name
nand_adq_i[15:0] Yes Yes NAND_ADQ[15:0]
nand_adq_oe Yes Yes
nand_adq_o[15:0] Yes Yes
nand_ale_o Yes Yes NAND_ALE
nand_ce_o[3:0] Yes, 4 chip enables Yes, 1 chip enable NAND_CE_N
nand_cle_o Yes Yes NAND_CLE
nand_re_o Yes Yes NAND_RE_N
nand_rdy_busy_i[3:0] Yes, 4 ready/busy signals Yes, 1 ready/busy signal NAND_RB
nand_we_o Yes Yes NAND_WE_N
nand_wp_o Yes Yes NAND_WP_N