Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

14.5. NAND Flash Controller Programming Model

This section describes how the NAND flash controller is to be programmed by software running on the microprocessor unit (MPU).
Note: If you write a configuration register and follow it up with a data operation that is dependent on the value of this configuration register, Intel recommends that you read the value of the register before performing the data operation. This read operation ensures that the posted write of the register is completed and takes effect before the data operation is issued to the NAND flash controller.

Basic Flash Programming

This section describes the steps that must be taken by the software to access and control the NAND flash controller.

NAND Flash Controller Optimization Sequence

The software must configure the flash device for interrupt or polling mode, using the bank0 bit of the rb_pin_enabled register in the config group. If the device is in polling mode, the software must also program the additional registers, to select the times and frequencies of the polling. Program the following registers in the config group:
  • Set the rb_pin_enabled register to the desired mode of operation for each flash device.
  • For polling mode, set the load_wait_cnt register to the appropriate value depending on the speed of operation of the NAND flash controller, and the desired wait value.
  • For polling mode, set the program_wait_cnt register to the appropriate value by software depending on the speed of operation of the NAND flash controller, and the desired wait value.
  • For polling mode, set the erase_wait_cnt register to the appropriate value by software depending on the speed of operation of the NAND flash controller, and the desired wait value.
  • For polling mode, set the int_mon_cyccnt register to the appropriate value by software depending on the speed of operation of the NAND flash controller, and the desired wait value.

At any time, the software can change any flash device from interrupt mode to polling mode or vice‑versa, using the bank0 bit of the rb_pin_enabled register.

The software must ensure that the particular flash device does not have any outstanding transactions before changing the mode of operation for that particular flash device.

Device Initialization Sequence

At initialization, the host software must program the following registers in the config group:
  • Set the devices_connected register to 1.
  • Set the device_width register to 8.
  • Set the device_main_area_size register to the appropriate value.
  • Set the device_spare_area_size register to the appropriate value.
  • Set the pages_per_block register according to the parameters of the flash device.
  • Set the number_of_planes register according to the parameters of the flash device.
  • If the device allows two ROW address cycles, the flag bit of the two_row_addr_cycles register must be set to 1. The host program can ensure this condition either of the following ways:
    • Set the flag bit of the bootstrap_two_row_addr_cycles register to 1 prior to the NAND flash controller’s reset initialization sequence, causing the flash controller to initialize the bit automatically.
    • Set the flag bit of the two_row_addr_cycles register directly to 1.
  • Clear the chip_enable_dont_care register in the config group to 0.

The NAND flash controller can identify the flash device features, allowing you to initialize the flash controller registers to interface correctly with the device, as described in Discovery and Initialization.

However, a few NAND devices do not follow any universally accepted identification protocol. If connected to such a device, the NAND flash controller cannot identify it correctly. If you are using such a device, your software must use other means to ensure that the initialization registers are set up correctly.

Device Operation Control

This section provides a list of registers that you need to program while choosing to use multi‑plane or cache operations on the device. If the device does not support multi‑plane operations or cache operations, then these registers can be left at their power‑on reset values with no impact on the functionality of the NAND flash controller. Even if the device supports these sequences, the software does not need to use them. Software can leave these registers at their power‑on reset values.

Program the following registers in the config group to achieve the best performance from a given device:

  • Set flag bit in the multiplane_operation register in the config group to 1 if the device supports multi‑plane operations to access the data on the flash device connected to the NAND flash controller. If the flash controller is set up for multi‑plane operations, the number of pages to be accessed is always a multiple of the number of planes in the device.
  • If the NAND flash controller is configured for multi‑plane operation, and if the device has support for multi‑plane read command sequence, set the multiplane_read_enable register in the config group.
  • If the device implements multiplane address restrictions, set the flag bit in the multiplane_addr_restrict register to 1.
  • Initialize the die_mask and first_block_of_next_plane registers as per device requirements.
  • If the device supports cache command sequences, enable the cache_write_enable and cache_read_enable registers in the config group.
  • Clear the flag bit of the copyback_disable register in the config group to 0 if the device does not support the copyback command sequences. The register defaults to enabled state.
  • The read_mode, write_mode and copyback_mode registers, in the config group, currently need not be written by software, because the NAND flash controller is capable of using the correct sequences based on a combination of some multi‑plane or cache‑related settings of the NAND flash controller and the manufacturer ID. If at some future time these settings change, program the registers to accommodate the change.

ECC Enabling

Before you start any data operation on the flash device, you must decide whether you want the ECC enabled or disabled.

To prevent spurious ECC errors, software must use the memory initialization block in the ECC controller to clear the entire memory data and initialize the ECC bits. The initialization block clears the memory data. Initializing the memory with the initialization block is independent of enabling the ECC.

If the ECC needs enabling, set up the appropriate correction level depending on the page size and the spare area available on the device.

Set the flag bit in the ecc_enable register in the config group to 1 to enable ECC. If enabled, the following registers in the config group must be programmed accordingly, else they can be ignored:

  • Initialize the ecc_correction register to the appropriate correction level.
  • Program the spare_area_skip_bytes and spare_area_marker registers in the config group if the software needs to preserve the bad block marker.

NAND Flash Controller Performance Registers

These registers specify the size of the bursts on the device interface, which maximizes the overall performance on the NAND flash controller.

Initialize the flash_burst_length register in the dma group to a value which maximizes the performance of the device interface by minimizing the number of bursts required to transfer a page.

Interrupt and DMA Enabling

Prior to initiating any data operation on the NAND flash controller, the software must set appropriate interrupt status register bits. If the software uses the DMA logic in the flash controller, then the appropriate DMA enable and interrupts bits in the register space must be set.
  1. Set the flag bit in the global_int_enable register in the config group to 1, to enable global interrupt.
  2. Set the relevant bits of the intr_en0 register in the status group to 1 before initiating any operations if the flash controller is in interrupt mode. Intel recommends that the software reads back this register to ensure clearing an interrupt status. This recommendation applies also to an interrupt service routine.
  3. Enable DMA if your application needs DMA mode. Enable DMA by setting the flag bit of the dma_enable register in the dma group. Intel recommends that the software reads back this register to ensure that the mode change is accepted before sending a DMA command to the flash controller.
  4. If the DMA is enabled, then set up the appropriate bits of the dma_intr_en register in the dma group.

Order of Interrupt Status Bits Assertion

The following interrupt status bits, in the intr_status0 register in the status group, are listed in the order of interrupt bit setting:
  1. time_out—All other interrupt bits are set to 0 when the watchdog time_out bit is asserted.
  2. dma_cmd_comp—This bit signifies the completion of data transfer sequence.32
  3. pipe_cpybck_cmd_comp—This bit is asserted when a copyback command or the last page of a pipeline command completes.
  4. locked_blk—This bit is asserted when a program (or erase) is performed on a locked block.
  5. INT_act—No relationship with other interrupt status bits. Indicates a transition from 0 to 1 on the ready_busy pin value for that flash device.
  6. rst_comp—No relationship with other interrupt status bits. Occurs after a reset command has completed.
  7. For an erase command:
    1. erase_fail (if failure)
    2. erase_comp
  8. For a program command:
    1. locked_blk (if performed on a locked block)
    2. pipe_cmd_err (if the pipeline sequence is broken by a MAP01 command)
    3. page_xfer_inc (at the end of each page data transfer)
    4. program_fail (if failure)
    5. pipe_cpybck_cmd_comp
    6. program_comp
    7. dma_cmd_comp (If DMA enabled)
  9. For a read command:
    1. pipe_cmd_err (if the pipeline sequence is broken by a MAP01 command)
    2. page_xfer_inc (at the end of each page data transfer)
    3. pipe_cpybck_cmd_comp
    4. load_comp
    5. ecc_uncor_error (if failure)
    6. dma_cmd_comp (If DMA enabled)

Timing Registers

You must optimize the following registers for your flash device’s speed grade and clock frequency. The NAND flash controller operates correctly with the power‑on reset values. However, functioning with power‑on reset values is a non‑optimal mode that provides loose timing (large margins to the signals).

Set the following registers in the config group to optimize the NAND flash controller for the speed grade of the connected device and frequency of operation of the flash controller:

  • twhr2_and_we_2_re
  • tcwaw_and_addr_2_data
  • re_2_we
  • acc_clks
  • rdwr_en_lo_cnt
  • rdwr_en_hi_cnt
  • max_rd_delay
  • cs_setup_cnt
  • re_2_re
Note:

In the case of the reading process mechanism, the NAND controller operates in two work modes: Boot mode and Performance mode.

After reset, the controller starts in Boot mode. In this mode, the data sampling doesn't depend on the default value of acc_clks or max_rd_delay registers but the correct sampling is warranted (with low performance) using the default values of the other registers listed above. The NAND controller remains in Boot mode as long as the value of acc_clks register remains in 0 (default value).

Once the acc_clks register takes a different value, the controller switches to Performance mode. In Performance mode, the data sampling on read operations now follows the functionality described in the acc_clks and max_rd_delay registers. The NAND controller remains in Performance mode until a reset occurs; for example, returning a value of 0 in acc_clks register doesn't make the controller to transit back to Boot mode again.

Registers to Ignore

You do not need to initialize the following registers in the config group:
  • The transfer_spare_reg register—Data transfer mode can be initialized using MAP10 commands.
  • The write_protect register—Does not need initializing unless you are testing the write protection feature.

Flash-Related Special Function Operations

This section describes all the special functions that can be performed on the flash memory.

The functions are defined by MAP10 commands as described in Command Mapping.

Erase Operations

Before data can be written to flash, an erase cycle must occur. The NAND flash memory controller supports single block and multi‑plane erases.

The controller decodes the block address from the indirect addressing shown in "MAP10 Command Format".

Single Block Erase

A single command is needed to complete a single‑block erase, as follows:
  1. Write to the command register, setting the CMD_MAP field to 2 and the BLK_ADDR field to the desired erase block.
  2. Write 0x01 to the Data register.

For a single block erase, the register multiplane_operation in the config group must be reset.

After the device completes the erase operation, the controller generates an erase_comp interrupt. If the erase operation fails, the erase_fail interrupt is issued. The failing block's address is updated in the err_block_addr0 register in the status group.

Multi-Plane Erase

For multi‑plane erases, the number_of_planes register in the config group holds the number of planes in the flash device, and the block address specified must be aligned to the number of planes in the device. The NAND flash controller consecutively erases each block of the memory, up to the number of planes available. Issue this command as follows:
  1. Write to the command register, setting the CMD_MAP field to 2 and the BLK_ADDR field to the desired erase block.
  2. Write 0x01 to the Data register.

For multi‑plane erase, the register multiplane_operation in the config group must be set.

After the device completes erase operation on all planes, the NAND flash controller generates an erase_comp interrupt. If the erase operation fails on any of the blocks in a multi‑plane erase command, an erase_fail interrupt is issued. The failing block's address is updated in the err_block_addr0 register in the status group.

Lock Operations

The NAND flash controller supports the following features:
  • Flash locking—The NAND flash controller supports all flash locking operations.

    The flash device itself might have limited support for these functions. If the device does not support locking functions, the flash controller ignores these commands.

  • Lock‑tight—With the lock‑tight feature, the NAND flash controller can prevent lock status from being changed. After the memory is locked tight, the flash controller must be reset before any flash area can be locked or unlocked.

Unlocking a Span of Memory Blocks

To unlock several blocks of memory, perform the following steps:
  1. Write to the command register, setting the CMD_MAP field to 2 and the BLK_ADDR field to the starting address of the area to unlock.
  2. Write 0x10 to the Data register.
  3. Write to the command register, setting the CMD_MAP field to 2 and the BLK_ADDR field to the ending address of the area to unlock.
  4. Write 0x11 to the Data register.

When unlocking a range of blocks, the start block address must be less than the end block address. Otherwise, the NAND flash controller exhibits undetermined behavior.

Locking All Memory Blocks

To lock the entire memory:
  1. Write to the command register, setting the CMD_MAP field to 2 and the BLK_ADDR field to any memory address.
  2. Write 0x21 to the Data register.

Setting Lock-Tight on All Memory Blocks

After the lock‑tight is applied, unlocked areas cannot be locked, and locked areas cannot be unlocked. To lock‑tight the entire memory:
  1. Write to the command register, setting the CMD_MAP field to 2 and the BLK_ADDR field to any memory address.
  2. Write 0x31 to the Data register.

To disable the lock‑tight, reset the memory controller.

Transfer Mode Operations

You can configure the NAND flash controller in one of the following modes of data transfer:
  • Default area transfer mode
  • Spare area transfer mode
  • Main+spare area transfer mode

The NAND flash controller determines the default transfer mode from the setting of transfer_spare_reg register in the config group. Use MAP10 commands to dynamically change the transfer mode from the existing mode to the new mode. All subsequent commands are in the new mode of transfer. You must consider that transfer modes can be changed at logical data transfer boundaries. For example:

  • At the beginning or end of a page in case of single page read or write.
  • At the beginning or end of a complete multi‑page pipeline read or write command.

transfer_spare_reg and MAP10 Transfer Mode Commands

The following table lists the functionality of the MAP10 transfer mode commands, and their mappings to the transfer_spare_reg register in the config group.
Table 134.  transfer_spare_reg and MAP10 Transfer Mode Commands
transfer_spare_reg MAP10 Transfer Mode Commands Resulting NAND Flash Controller Mode

0

0x42

Main33

0

0x41

Spare

0

0x43

Main+spare

1

0x42

Main+spare33

1

0x41

Spare

1

0x43

Main+spare

Configure for Default Area Access

You only need to configure for default area access if the transfer mode was previously changed to spare area or main+spare area. To configure default area access:
  1. Write to the command register, setting the CMD_MAP field to 2 and the BLK_ADDR field to any block.
  2. Write 0x42 to the Data register.

The NAND flash controller determines the default area transfer mode from the setting of the transfer_spare_reg register in the config group. If it is set to 1, then the transfer mode becomes main+spare area, otherwise it is main area.

Configure for Spare Area Access

To access only the spare area of the flash device, use the MAP10 command to set up the NAND flash controller to read or write only the spare area on the device. After the flash controller is set up, use MAP01 read and write commands to access the spare area of the appropriate block and page addresses. To configure the NAND flash controller to access the spare area only, perform the following steps:
  1. Write to the command register, setting the CMD_MAP field to 2 and the BLK_ADDR field to the target block.
  2. Write 0x41 to the Data register.

Configure for Main+Spare Area Access

To configure the NAND flash controller to access the main+spare area:
  1. Write to the command register, setting the CMD_MAP field to 2 and the BLK_ ADDR field to the target block.
  2. Write 0x43 to the Data register.

Read-Modify-Write Operations

To read a specific page or modify a few words, bytes, or bits in a page, use the RMW operations. A read command copies the desired data from flash memory to a page buffer. You can then modify the information in the buffer using MAP00 buffer read and write commands and issue another command to write that information back to the memory.

The read‑modify‑write command operates on an entire page. This command is also useful for a copy type operation, where most of a page is saved to a new location. In this type of operation, the NAND flash controller reads the data, modifies a specified number of words in the page, and then writes the modified page to a new location.

Note: Because the data is modified within the page buffer of the flash device, the NAND flash controller ECC hardware is not used in RMW operations. Software must update the ECC during RMW operations.
Note: For a read‑modify‑write command to work with hardware ECC, the entire page must be read into system memory, modified, then written back to flash without relying on the RMW feature.

Read-Modify-Write Operation Flow

  1. Start the flow by reading a page from the memory:
    • Write to the command register, setting the CMD_MAP field to 2 and the BLK_ADDR field to the starting address of the desired block.
    • Write 0x60 to the Data register.
    This step makes the page available to you in the page buffer in the flash device.
  2. Provide the destination page address:
    • Write to the command register, setting the CMD_MAP field to 2 and the BLK_ADDR field to the destination address of the desired block.
    • Write 0x61 to the Data register.
    This step initiates the page program and provides the destination address to the device.
  3. Use the MAP00 page buffer read and write commands to modify the data in the page buffer.
  4. Write the page buffer data back to memory:
    • Write to the command register, setting the CMD_MAP field to 2 and the BLK_ADDR field to the same destination address.
    • Write 0x62 to the Data register.
    This step performs the write.

After the device completes the load operation, the NAND flash controller issues a load_comp interrupt. A program_comp interrupt is issued when the host issues the write command and the device completes the program operation.

If the page program operation (as a part of an RMW operation) results in a program failure in the device, program_fail interrupt is issued. The failing page's block and page address is updated in the err_block_addr0 and err_page_addr0 registers in the status group.

Copy-Back Operations

The NAND flash controller supports copy back operations. However, the flash device might have limited support for this function. If you attempt to perform a copy‑back operation on a device that does not support copy‑back, the NAND flash controller triggers an interrupt. An interrupt is also triggered if the source block is not specified before the destination block is specified, or if the destination block is not specified in the next command following a source block specification.

The NAND flash controller cannot do ECC validation in case of copy‑back commands. The flash controller copies the ECC data, but does not check it during the copy operation.

Note: Intel recommends that you use copy‑back only if the ECC implemented in the flash controller is strong enough so that the next access can correct accumulated errors.

The 8‑bit value <PP> specifies the number of pages for copy‑back. With this feature, the NAND flash controller can copy multiple consecutive pages with a single command. When you issue a copy‑back command, the flash controller performs the operation in the background. The flash controller puts other commands on hold until the current copy‑back completes.

For a multi‑plane device, if the flag bit in the multiplane_operation register in the config group is set to 1, multi‑plane copy‑back is available as an option. In this case, the block address specified must be plane‑aligned and the value <PP> must specify the total number of pages to copy as a multiple of the number of planes. The block address continues incrementing, keeping the page address fixed, for the total number of planes in the device before incrementing the page address.

A pipe_cpyback_cmd_comp interrupt is generated when the flash controller has completed copy‑back operation of all <PP> pages. If any page program operation (as a part of copy back operation) results in a program failure in the device, the program_fail interrupt is issued. The failing page's block and page address is updated in the err_block_addr0 and err_page_addr0 registers in the status group.

Copying a Memory Area (Single Plane)

To copy <PP> pages from one memory location to another:
  1. Write to the command register, setting the CMD_MAP field to 2 and the BLK_ADDR field to the starting address of the area to be copied.
  2. Write 0x1000 to the Data register.
  3. Write to the command register, setting the CMD_MAP field to 2 and the BLK_ADDR field to the starting address of the new area to be written.
  4. Write 0x11<PP> to the Data register, where <PP> is the number of pages to copy.

Copying a Memory Area (Multi-Plane)

To copy <PP> pages from one memory location to another:
  1. Set the flag bit of the multiplane_operation register in the config group to 1.
  2. Write to the command register, setting the CMD_MAP field to 2 and the BLK_ADDR field to the starting address of the area to be copied. The address must be plane‑aligned.
  3. Write 0x1000 to the Data register.
  4. Write to the command register, setting the CMD_MAP field to 2 and the BLK_ADDR field to the starting address of the new area to be written. This address must also be plane‑aligned.
  5. Write 0x11<PP> to the Data register, where <PP> is the number of pages to copy.

The parameter <PP> must be a multiple of the number of planes in the device.

Pipeline Read-Ahead and Write-Ahead Operations

The NAND flash controller supports pipeline read‑ahead and write‑ahead operations. However, the flash device might have limited support for this function. If the device does not support pipeline read‑ahead or write‑ahead, the flash controller processes these commands as standard reads or writes.

The NAND flash controller can handle at the most four outstanding pipeline commands, queued up in the order in which the flash controller received the commands. The flash controller operates on the pipeline command at the head of the queue until all the pages corresponding to the pipeline command are executed. The flash controller then pops the pipeline command at the head of the queue and proceeds to work on the next pipeline command in the queue.

Pipeline Read-Ahead Function

The pipeline read‑ahead function allows for a continuous reading of the flash memory. On receiving a pipeline read command, the flash controller immediately issues a load command to the device. While data is read out with MAP01 commands in a consecutive or multi‑plane address pattern, the flash controller maintains additional cache or multi‑plane read command sequencing for continuous streaming of data from the flash device.

Pipeline read‑ahead commands can read data from the queue in this interleaved fashion. The parameter <PP> denotes the total number of pages in multiples of the number of planes available, and the block address must be plane‑aligned, which keeps the page address constant while incrementing the block address for each page‑size chunk of data. After reading from every plane, the NAND flash controller increments the page address and resets the block address to the initial address. You can also use pipeline write‑ahead commands in multi‑plane mode. The write operation works similarly to the read operation, holding the page address constant while incrementing the block address until all planes are written.

Note: The same four‑entry queue is used to queue the address and page count for pipeline read‑ahead and write‑ahead commands. This commonality requires that you use MAP01 commands to read out all pages for a pipeline read‑ahead command before the next pipeline command can be processed. Similarly, you must write to all pages pertaining to pipeline write‑ahead command before the next pipeline command can be processed.

Because the value of the flag bit of the multiplane_operation register in the config group determines pipeline read‑ahead or write‑ahead behavior, it can only be changed when the pipeline registers are empty.

When the host issues a pipeline read‑ahead command, and the flash controller is idle, the load operation occurs immediately.

Note: The read‑ahead command does not return the data to the host, and the write‑ahead command does not write data to the flash address. The NAND flash controller loads the read data. The read data is returned to the host only when the host issues MAP01 commands to read the data. Similarly, the flash controller loads the write data, and writes it to the flash only when the host issues MAP01 commands to write the data.
Set Up a Single Area for Pipeline Read-Ahead
To set up an area for pipeline read‑ahead, perform the following steps:
  1. Write to the command register, setting the CMD_MAP field to 2 and the BLK_ADDR field to the starting address of the block to pre‑read.
  2. Write 0x20<PP> to the Data register, where the 0 sets this command as a read‑ahead and <PP> is the number of pages to pre‑read. The pages must not cross a block boundary. If a block boundary is crossed, the NAND flash controller generates an unsupported command (unsup_cmd) interrupt and drops the command.

The read‑ahead command is a hint to the flash device to start loading the next page in the page buffer as soon as the previous page buffer operation has completed. After you set up the read‑ahead, use a MAP01 command to actually read the data. In the MAP01 command, specify the same starting address as in the read‑ahead.

If the read command received following a pipeline read‑ahead request is not to a pre‑read page, then an interrupt bit is set to 1 and the pipeline read‑ahead or write‑ahead registers are cleared. You must issue a new pipeline read‑ahead request to re‑load the same data. You must use MAP01 commands to read all of the data that is pre‑read before the NAND flash controller returns to the idle state.

Pipeline Write-Ahead Function

The pipeline write‑ahead function allows for a continuous writing of the flash memory. While data is written with MAP01 commands in a consecutive or multi‑plane address pattern, the NAND flash controller maintains cache or multi‑plane command sequences for continuous streaming of data into the flash device.

For pipeline write commands, if any page program results in a failure in the device, a program_fail interrupt is issued. The failing page's block and page addresses are updated in the err_block_addr0 and err_page_addr0 registers in the status group.

Set Up a Single Area for Pipeline Write-Ahead
To set up an area for pipeline write‑ahead:
  1. Write to the command register, setting the CMD_MAP field to 2 and the BLK_ADDR field to the starting address of the block to pre‑write.
  2. Write 0x21<PP> to the Data register, where the value 1 sets this command as a write‑ahead and <PP> is the number of pages to pre‑write. The pages must not cross a block boundary. If a block boundary is crossed, the NAND flash controller generates an unsupported command (unsup_cmd) interrupt and drops the command.

After you set up the write‑ahead, use a MAP01 command to write the data. In the MAP01 command, specify the same starting address as in the write‑ahead.

If the write command received following a pipeline write‑ahead request is not to a pre‑written page, then an interrupt bit is set to 1 and the pipeline read‑ahead or write‑ahead registers are cleared. You must issue a new pipeline write‑ahead request to configure the write logic.

You must use MAP01 commands to write all of the data that is pre‑written before the NAND flash controller returns to the idle state.

Other Supported Commands

MAP01 commands must read or write pages in the same sequence that the pipelined commands were issued to the NAND flash controller. If the host issues multiple pipeline commands, pages must be read or written in the order the pipeline commands were issued. It is not possible to read or write pages for a second pipeline command before completing the first pipeline command. If the pipeline sequence is broken by a MAP01 command, the pipe_cmd_err interrupt is issued, and the flash controller clears the pipeline command queue. The flash controller services the violating incoming MAP01 read or write request with a normal page read or write sequence.

For a multi‑plane device that supports multi‑plane programming, you must set the flag bit of the multiplane_operation register in the config group to 1. In this case, the data is interleaved into page‑size chunks to consecutive blocks.

A pipe_cpyback_cmd_comp interrupt is generated when the NAND flash controller has finished processing a pipeline command and has discarded that command from its queue. At this point of time, the host can send another pipeline command. A pipeline command is popped from the queue, and an interrupt is issued when the flash controller has started processing the last page of pipeline command. Hence, the pipe_cpyback_cmd_comp interrupt is issued prior to the last page load in the case of a pipeline read command and start of data transfer of the last page to be programmed, in the case of a pipeline write command.

An additional program_comp interrupt is generated when the last page program operation completes in the case of a pipeline write command.

If the device command set requires the NAND flash controller to issue a load command for the last page in the pipeline read command, a load_comp interrupt is generated after the last page load operation completes.

The pipeline commands sequence advanced commands in the device, such as cache and multi‑plane. When the NAND flash controller receives a multi‑page read or write pipeline command, it sequences commands sent to the device depending on settings in the following registers in the config group:

  • cache_read_enable
  • cache_write_enable
  • multiplane_operation

For a device that supports cache read sequences, the flag bit of the cache_read_enable register must be set to 1. The NAND flash controller sequences each multi‑page pipeline read command as a cache read sequence. For a device that supports cache program command sequences, cache_write_enable must be set. The flash controller sequences each multi‑page write pipeline command as a cache write sequence.

For a device that has multi‑planes and supports multi‑plane program commands, the NAND flash controller register multiplane_operation, in the config group, must be set. On receiving the multi‑page pipeline write command, the flash controller sequences the device with multi‑plane program commands and expects that the host transfers data to the flash controller in an even‑odd block increment addressing mode.

32 This interrupt status bit is the last to be asserted during a DMA operation to transfer data.
33 Default access mode (0x42) maps to either main (only) or main+spare mode, depending on the value of transfer_spare_reg.