Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

8.1.1. Features of the System Interconnect

The system interconnect supports high-throughput peripheral devices. The system interconnect has the following characteristics:

  • Byte oriented address handling
  • Data bus width up to 128 bits
  • Arm* TrustZone* -compliant firewall and security support, with additional security features configurable per master
  • Programmable quality-of-service (QoS) optimization
  • Dedicated SDRAM L3 interconnect, providing access and scheduling for the hard memory controller in the FPGA portion of the SoC device
  • On-chip debug and tracing capabilities
  • Multiple independent L4 buses with independent clock domains and protocols

    The L4 buses are each connected to a master in the main L3 interconnect for control and status register access. Each L4 bus is 32 bits wide and is connected to multiple slaves. The L4 buses also provide a low- to mid-level tier of the system interconnect for lower-bandwidth slave peripherals. Each L4 bus is 32 bits wide and operates in a separate clock domain.