Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

8.2.1.1. Arria 10 HPS Available Address Maps

The following figure shows the default system interconnect address maps for all masters. The figure is not to scale.
Figure 36. Address Maps for System Interconnect Masters

Notes on Address Maps

(1) Transactions on these addresses are directly decoded by the SCU and L2 cache.

(2) The MPU accesses SDRAM through a dedicated port to the SDRAM scheduler. The SDRAM window size also depends on L2 cache filtering.

(3) This region can be configured to access on-chip RAM, by using the noc_addr_remap_value, noc_addr_remap_set, and noc_addr_remap_clear registers, in the system manager.

(4) The following peripherals can master the interconnect:

  • Ethernet MACs
  • USB-2.0 OTG controllers
  • NAND controller
  • ETR
  • SD/MMC controller

4To access registers that are connected to the HPS-to-FPGA AXI* master bridge, you need to set the base address of your slave interface starting from 0xC0000000. The HPS-to-FPGA AXI* master bridge can be connected to any type of slave interface such as APB* and Avalon® .

For the MPU L3 master, either the boot ROM or on-chip RAM can map to address 0x0 and obscure the lowest 128 KB or 256 KB of SDRAM.

At boot time, the MPU does not have access to the SDRAM address space from the top of ROM or on-chip RAM to 0x00100000. This is because the MPU's SDRAM access is controlled by the MPU L2 filter registers, which only have a granularity of 1 MB. After booting completes, the MPU can change address filtering to use the lowest 1 MB of SDRAM.

For non-MPU masters, either the on-chip RAM or the SDRAM maps to address 0x0. When mapped to address 0x0, the on-chip RAM obscures the lowest 256 KB of SDRAM for non-MPU masters.