Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

13.2.2. Boot ROM Block Diagram and System Integration

Figure 58. Block diagram of On-Chip ROM

Boot ROM and L3 interconnect transfers data through a 32-bit data interface that passes through a firewall, operating at the l3_main_free_clk interconnect clock frequency. The memory has a read acceptance of one, a write acceptance of one, and a total acceptance of two with round-robin arbitration.