Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

3.3.1.1. PLLs

The two PLLs in the clock manager generate the majority of clocks in the HPS. There is no phase control between the clocks generated by the two PLLs.

Each PLL has the following features:

  • Phase detector and output lock signal generation
  • Registers to set VCO frequency
    • Multiplier range is 1 to 4096
    • Divider range is 1 to 64
  • 16 post-scale counters (C0-C8) with a range of 1 to 2048 to further subdivide the clock
  • A PLL can be enabled to bypass all outputs to the input clock for glitch-free transitions