Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

8. System Interconnect

The components of the hard processor system (HPS) communicate with one another, and with other portions of the SoC device, through the system interconnect. The system interconnect consists of the following blocks:

  • The main level 3 (L3) interconnect
  • The SDRAM L3 interconnect
  • The level 4 (L4) buses

The system interconnect is the main communication bus for the MPU and all IPs in the SoC device.

The system interconnect is implemented by the Arteris® FlexNoC™ network-on-chip (NoC) interconnect module.

The system interconnect supports the following features:

  • An L3 interconnect that provides high-bandwidth routing between masters and slaves in the HPS
  • SDRAM L3 interconnect, providing access to a hard memory controller in the FPGA fabric through a multiport front end (MPFE) scheduler for sharing the external SDRAM between multiple masters in the SoC device
  • Independent L4 buses running in several clock domains. These buses handle data traffic for low- to mid-level bandwidth slave peripherals and accesses to peripheral control and status registers throughout the address map.
  • On-chip debugging and tracing capabilities
  • Security firewalls with the following capabilities:
    • Secure or nonsecure access configured per peripheral
    • Privileged or user access configured per peripheral (for some peripherals)
    • Security optionally configured per transaction at the master
  • Quality of service (QoS) with three programmable levels of service on a per-master basis