Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

14.4.10.2.2. Spare Area Transfer Mode

The NAND flash controller does not introduce or interpret ECC check bits in spare area transfer mode, and acts as a pass-through for data transfer.
Note: If you require the spare area to be protected, a software implementation is required.
Figure 61. Spare Area Transfer Mode for ECC