Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

18.3.2. FPGA EMAC I/O Signals

Three Ethernet Media Access Controllers are provided in the HPS. The table below describes the signals that are available from each Ethernet Media Access Controller to the FPGA I/O. For more information on routing EMAC signals to the FPGA and HPS I/O, refer to the HPS Component Interfaces chapter. See the HPS I/O table for general clock to data relationships across the modes.

Table 179.  FPGA EMAC I/O Signals

Signal Name

In/Out

Width

Description

emac_clk_tx_i

Transmit Clock

In

1

This is the transmit clock (2.5 MHz/25 MHz) provided by the MII PHYs only. This clock comes from the FPGA Interface and is used for TX data capture. This clock is not used in GMII mode.

Note: This clock must be able to perform glitch free switching between 2.5 and 25 MHz.
emac_phy_txclk_o

Transmit Clock Output

Out

1

In GMII mode, this signal is the transmit clock output to the PHY to sample data.

For MII, this clock is unused.

emac_phy_txd_o[7:0]

PHY Transmit Data

Out

8

These are a group of eight transmit data signals driven by the EMAC.

All eight bits provide the GMII transmit data byte. For the lower speed MII operation, only bits[3:0] are used. The validity of the data is qualified with phy_txen_o and phy_txer_o. Synchronous to phy_txclk_o.

emac_phy_txen_o

PHY Transmit Data Enable

Out

1

This signal is driven by the EMAC and is used in GMII mode. When driven high, this signal indicates that valid data is being transmitted on the clk_tx_o bus.

emac_phy_txer_o

PHY Transmit Error

Out

1

This signal is driven by the EMAC and when high, indicates a transmit error or carrier extension on the phy_txd bus. It is also used to signal low power states in Energy Efficient Ethernet operation.

emac_rst_clk_tx_n_o

Transmit Clock Reset output

Out

1

Transmit clock reset output to the FPGA fabric, which is the internal synchronized reset to clk_tx_int output from the EMAC. May be used by logic implemented in the FPGA fabric as desired.

The reset pulse width of the rst_clk_tx_n_o signal is three transmit clock cycles.

emac_clk_rx_i

Receive Clock

In

1

Receive clock from external PHY.

For GMII, the clock frequency is 125 MHz. For MII, the receive clock is 25 MHz for 100 Mbps and 2.5 MHz for 10 Mbps.

emac_phy_rxd_i[7:0]

PHY Receive Data

In

8

This is an eight-bit receive data bus from the PHY. In GMII mode, all eight bits are sampled. The validity of the data is qualified with phy_rxdv_i and phy_rxer_i. For lower speed MII operation, only bits [3:0] are sampled. These signals are synchronous to phy_clk_rx_i.

emac_phy_rxdv_i

PHY Receive Data Valid

In

1

This signal is driven by PHY. In GMII mode, when driven high, it indicates that the data on the phy_rxd bus is valid. It remains asserted continuously from the first recovered byte of the frame through the final recovered byte.

emac_phy_rxer_i

PHY Receive Error

In

1

This signal indicates an error or carrier extension (GMII) in the received frame. This signal is synchronous to phy_clk_rx_i.

emac_rst_clk_rx_n_o

Receive clock reset output.

Out

1

Receive clock reset output.

The reset pulse width of the rst_clk_rx_n_o signal is three transmit clock cycles.

emac_phy_mac_speed_o[1:0] EMAC Speed Out 2 This signal indicates the 10-Mbps, 100-Mbps or 1000-Mbps operating speed and reflects the Port Select and FES bit of the MAC Configuration register. The signal value encodings are:
  • 0x0: 1000 Mbps (GMII)
  • 0x1: 1000 Mbps (GMII)
  • 0x2: 10 Mbps (MII)
  • 0x3: 100 Mbps (MII)
emac_phy_crs_i

PHY Carrier Sense

In

1

This signal is asserted by the PHY when either the transmit or receive medium is not idle. The PHY de-asserts this signal when both transmit and receive interfaces are idle. This signal is not synchronous to any clock.

emac_phy_col_i

PHY Collision Detect

In

1

This signal, valid only when operating in half duplex, is asserted by the PHY when a collision is detected on the medium. This signal is not synchronous to any clock.