Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

11.5.1. Coresight Component Address

CoreSight components are configured through memory-mapped registers, located at offsets relative to the CoreSight component base address. CoreSight component base addresses are accessible through the component address table in the DAP ROM.

Table 104.  Coresight Component Address TableThe following table is located in the ROM table portion of the DAP.

ROM Entry

Offset[30:12]

Description

0x0

0x00001

ETF Component Base Address

0x1

0x00002

CTI Component Base Address

0x2

0x00003

TPIU Component Base Address

0x3

0x00004

Trace Funnel Component Base Address

0x4

0x00005

STM Component Base Address

0x5

0x00006

ETR Component Base Address

0x6

0x00007

FPGA‑CTI Component Base Address

0x7

0x00100

A9 ROM

0x8

0x00080

FPGA ROM

0x9

0x00008

L3-CTI

A host debugger can access this table at 0x80000000 through the DAP. HPS masters can access this ROM at 0xFF000000. Registers for a particular CoreSight component are accessed by adding the register offset to the CoreSight component base address, and adding that total to the base address of the ROM table.

The base address of the ROM table is different when accessed from the debugger (at 0x8000_0000) than when accessed from any HPS master (at 0xFF000000). For example, the CTI output enable (CTIOUTEN) register, CTIOUTEN[2] at offset 0xA8, can be accessed by the host debugger at 0x800020A8. To derive that value, add the host debugger access address to the ROM table of 0x80000000, to the CTI component base address of 0x00002000, to the CTIOUTEN[2] register offset of 0xA8.