Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

10.3.15.5.1. Recommended Burst Types

Table 92.  Recommended Burst Types for Optimized Bursts

Burst Type

Beats

Width (Bits)

Address Type

Byte Strobes

Wrapping

4

64

64‑bit aligned

Asserted

Incrementing

4

64

32‑bit aligned

Asserted

Note: If the slave port of the FPGA-to-HPS bridge is not 64 bits wide, you must supply bursts to the FPGA‑to‑HPS bridge that are upsized or downsized to the burst types above. For example, if the slave data width of the FPGA‑to‑HPS bridge is 32 bits, then bursts of eight beats by 32 bits are required to access the ACP efficiently.
Note: If the address and burst size of the transaction to the ACP matches either of the conditions shown in the table "Recommended Burst Types for Optimized Bursts", the logic in the MPU assumes the transaction has all its byte strobes set. If the byte strobes are not all set, then the write does not actually overwrite all the bytes in the word. Instead, the cache assumes the whole cache line is valid. If this line is dirty (and therefore gets written out to SDRAM), data corruption might occur.

In addition to optimizing performance, using a 64-bit access width will allow you to use ECC. ECC is only supported for 64-bit accesses that are 64-bit aligned..